llvm-svn: 123986

llvm-svn: 123985

then doing a thread step-out.  This should lead us to the caller frame of the
frame we just selected.

llvm-svn: 123984

llvm-svn: 123983

NRVO candidate for a return statement, to
Sema::getCopyElisionCandidate(), and teach it enough to also determine
the NRVO candidate for a throw expression. We still don't use the
latter information, however.

Along the way, implement core issue 1148, which eliminates copy
elision from catch parameters and clarifies that copy elision cannot
occur from function parameters (which we already implemented).

llvm-svn: 123982

f(T&) and f(T&&).

llvm-svn: 123981

this example further as more rvalue-reference features come online.

llvm-svn: 123980

reference to an rvalue rather than binding a const-qualified lvalue
reference to that rvalue.

llvm-svn: 123979

llvm-svn: 123978

resolution to match the latest C++0x working paper's semantics. The
implementation now matching up with the reference-binding
implementation used for initialization.

llvm-svn: 123977

Patch by arrowdodger!

llvm-svn: 123976

qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975

llvm-svn: 123974

instructions.

llvm-svn: 123973

This reverts commit 281f3901b7b0869929caf8946c1ad1228bc38922.

llvm-svn: 123972

DAG. Disable using "-disable-sched-cycles".

For ARM, this enables a framework for modeling the cpu pipeline and
counting stalls. It also activates several heuristics to drive
scheduling based on the model. Scheduling is inherently imprecise at
this stage, and until spilling is improved it may defeat attempts to
schedule. However, this framework provides greater control over
tuning codegen.

Although the flag is not target-specific, it should have very little
affect on the default scheduler used by x86. The only two changes that
affect x86 are:
- scheduling a high-latency operation bumps the current cycle so independent
  operations can have their latency covered. i.e. two independent 4
  cycle operations can produce results in 4 cycles, not 8 cycles.
- Two operations with equal register pressure impact and no
  latency-based stalls on their uses will be prioritized by depth before height
  (height is irrelevant if no stalls occur in the schedule below this point).

llvm-svn: 123971

select frame #3, you can then do a step out and be able to go directly to the
frame above frame #3! 

Added StepOverUntil and StepOutOfFrame to the SBThread API to allow more powerful
stepping.

llvm-svn: 123970

flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.

llvm-svn: 123969

llvm-svn: 123968

llvm-svn: 123967

call (C++0x [temp.deduct.call]p3).

As part of this, start improving the reference-binding implementation
used in the computation of implicit conversion sequences (for overload
resolution) to reflect C++0x semantics. It still needs more work and
testing, of course.

llvm-svn: 123966

llvm-svn: 123965

llvm-svn: 123964

a select. A vector select is pairwise on each element so we'd need a new
condition with the right number of elements to select on. Fixes PR8994.

llvm-svn: 123963

llvm-svn: 123962

This allows us to simplify the handling for the overloadable attribute,
removing a number of FIXMEs.

llvm-svn: 123961

llvm-svn: 123960

Inheritable attributes on declarations may be inherited by any later
redeclaration at merge time.  By contrast, a non-inheritable attribute
will not be inherited by later redeclarations.  Non-inheritable
attributes may be semantically analysed early, allowing them to
influence the redeclaration/overloading process.

Before this change, the "overloadable" attribute received special
handling to be treated as non-inheritable, while all other attributes
were treated as inheritable.  This patch generalises the concept,
while removing a FIXME.  Some CUDA location attributes are also marked
as non-inheritable in order to support special overloading semantics
(to be introduced in a later patch).

The patch introduces a new Attr subclass, InheritableAttr, from
which all inheritable attributes derive.  Non-inheritable attributes
simply derive from Attr.

N.B. I did not review every attribute to determine whether it should
be marked non-inheritable.  This can be done later on an incremental
basis, as this change does not affect default functionality.

llvm-svn: 123959

This patch makes the necessary changes to TableGen to support
non-inheritable attributes.

llvm-svn: 123958

circumstances.

llvm-svn: 123957

While here, I'd like to complain about how vector is not an aggregate type
according to llvm::Type::isAggregateType(), but they're listed under aggregate
types in the LangRef and zero vectors are stored as ConstantAggregateZero.

llvm-svn: 123956

Add more reference-binding examples from the C++0x working paper, all of which seem to be working fine

llvm-svn: 123955

Improve on test case. Per Doug's comment. wip.

llvm-svn: 123954

reference to an lvalue.

llvm-svn: 123953

specification. In particular, an rvalue reference can bind to an
initializer expression that is an lvalue if the referent type and the
initializer expression type are not reference-related. This is a newer
formulation to the previous "rvalue references can never bind to
lvalues" rule.

llvm-svn: 123952

type checking based on the actual reference type we're trying to bind
the result to, rather than stripping the reference.

llvm-svn: 123950

value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.

llvm-svn: 123949

llvm-svn: 123948

llvm-svn: 123947

llvm-svn: 123944