- Jul 16, 2012
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Evan Cheng authored
uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 llvm-svn: 160312
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Nadav Rotem authored
llvm-svn: 160311
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Simon Atanasyan authored
The first variant accepts immediate number as the second argument. The second variant accepts register operand as the second argument. llvm-svn: 160307
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Nadav Rotem authored
Make ComputeDemandedBits return a deterministic result when computing an AssertZext value. In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160305
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Tom Stellard authored
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
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Tom Stellard authored
This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc. llvm-svn: 160302
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Tom Stellard authored
This reverts commit e3013202259ed1e006c21817c63cf25d75982721. llvm-svn: 160301
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Tom Stellard authored
This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea. llvm-svn: 160300
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Tom Stellard authored
Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>" This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590. llvm-svn: 160299
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Tom Stellard authored
This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2. llvm-svn: 160298
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Tom Stellard authored
This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a. llvm-svn: 160297
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Tom Stellard authored
Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0)." This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe. llvm-svn: 160296
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Tom Stellard authored
This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6. llvm-svn: 160295
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Nuno Lopes authored
Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients llvm-svn: 160294
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Chad Rosier authored
llvm-svn: 160293
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Kostya Serebryany authored
[asan] a bit more refactoring, addressed some of the style comments from chandlerc, partially implemented crash callback merging (under flag) llvm-svn: 160290
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Aaron Ballman authored
MSVC's implementation of isalnum will assert on characters > 255, so we need to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll llvm-svn: 160286
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Kostya Serebryany authored
[asan] refactor instrumentation to allow merging the crash callbacks (not fully implemented yet, no functionality change except the BB order) llvm-svn: 160284
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NAKAMURA Takumi authored
llvm-svn: 160280
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NAKAMURA Takumi authored
Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0). llvm-svn: 160279
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NAKAMURA Takumi authored
llvm-svn: 160278
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Jack Carter authored
Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. llvm-svn: 160277
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NAKAMURA Takumi authored
llvm-svn: 160276
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NAKAMURA Takumi authored
Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h> llvm-svn: 160275
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Alexey Samsonov authored
1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp. 2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of vector add. llvm-svn: 160274
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Tom Stellard authored
llvm-svn: 160273
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Tom Stellard authored
llvm-svn: 160272
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Tom Stellard authored
llvm-svn: 160271
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Tom Stellard authored
llvm-svn: 160270
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Kostya Serebryany authored
llvm-svn: 160269
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Nadav Rotem authored
undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160260
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Chandler Carruth authored
It turns out that ASan relied on the at-the-end block insertion order to (purely by happenstance) disable some LLVM optimizations, which in turn start firing when the ordering is made more "normal". These optimizations in turn merge many of the instrumentation reporting calls which breaks the return address based error reporting in ASan. We're looking at several different options for fixing this. llvm-svn: 160256
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Chandler Carruth authored
This is particularly useful to the backend code generators which try to process things in the incoming function order. Also, cleanup some uses of IRBuilder to be a bit simpler and more clear. llvm-svn: 160254
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Chandler Carruth authored
functionality test. In general, unless the functionality is substantially separated, we should lump more basic testing into this file. The test running infrastructure likes having a few test files with more comprehensive testing within them. llvm-svn: 160253
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Chandler Carruth authored
Added a basic unit test for this with CreateCondBr. I didn't go all the way and test the switch side as the boilerplate for setting up the switch IRBuilder unit tests is a lot more. Fortunately, the two share all the interesting code paths. llvm-svn: 160251
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Chandler Carruth authored
This is in anticipation of changing CreateCondBr and wanting to test those changes. llvm-svn: 160250
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Chandler Carruth authored
the original move of IRBuilder. llvm-svn: 160249
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Alexey Samsonov authored
It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. llvm-svn: 160248
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Chandler Carruth authored
the move of *Builder classes into the Core library. No uses of this builder in Clang or DragonEgg I could find. If there is a desire to have an IR-building-support library that contains all of these builders, that can be easily added, but currently it seems likely that these add no real overhead to VMCore. llvm-svn: 160243
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Chandler Carruth authored
llvm-svn: 160242
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