llvm-svn: 83207

operands of instructions with these properties while breaking anti-dep.

llvm-svn: 83198

llvm-svn: 83190

If location info is attached with an instruction then keep track of alloca slots used by a variable. This info will be used by AsmPrinter to emit debug info for variables.

llvm-svn: 83189

This will allow processDebugLoc() to handle scopes for DWARF debug info. 

llvm-svn: 83183

llvm-svn: 83182

llvm-svn: 83181

to emit target-specific things at the beginning of the asm output.  This
fixes a problem for PPC, where the text sections are not being kept together
as expected.  The base class doInitialization code calls DW->BeginModule()
which emits a bunch of DWARF section directives.  The PPC doInitialization
code then emits all the TEXT section directives, with the intention that they
will be kept together. But as I understand it, the Darwin assembler treats
the default TEXT section as a special case and moves it to the beginning of
the file, which means that all those DWARF sections are in the middle of
the text.  With this change, the EmitStartOfAsmFile hook is called before
the DWARF section directives are emitted, so that all the PPC text section
directives come out right at the beginning of the file.

llvm-svn: 83176

llvm-svn: 83171

llvm-svn: 83164

llvm-svn: 83163

basic blocks that are so long that their size overflows a short.

Also assert that overflow does not happen in the future, as requested by Evan.

This fixes PR4401.

llvm-svn: 83159

llvm-svn: 83144

per customary usage

llvm-svn: 83137

llvm-svn: 83132

llvm-svn: 83123

Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.

llvm-svn: 83122

information.  This allows arbitrary code involving DW_OP_plus_uconst
and DW_OP_deref.  The scheme allows for easy extention to include,
any, or all of the DW_OP_ opcodes.  I thought about just exposing all
of them, but, wasn't sure if people wanted the dwarf opcodes exposed
in the api.  Is that a layering violation?

With this scheme, the entire existing block scheme used by llvm-gcc
can be switched over to the new scheme.  I think that would be
cleaner, as then the compiler specific bits are not present in llvm
proper.  Before the old code can be yanked however, similar code in
clang would have to be removed.

Next up, more testing.

llvm-svn: 83120

llvm-svn: 83103

Remove unnecessary cast.

llvm-svn: 83100

llvm-svn: 83083

so a simple "current register" will suffice. Also add some additional
sanity-checking assertions to make sure things are as we expect.

llvm-svn: 83081

the instruction we're scavenging for. The scavenger needs to know to avoid
them when analyzing register usage.

llvm-svn: 83077

llvm-svn: 83019

llvm-svn: 83016

llvm-svn: 83007

llvm-svn: 82995

physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.

llvm-svn: 82968

llvm-svn: 82909

where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. 

llvm-svn: 82861

allocatable. Even if it doesn't appear to have any defs, it may latter
on after register allocation.

llvm-svn: 82834

llvm-svn: 82825

MathExtras.h in MachineMemOperand.h.

llvm-svn: 82822

llvm-svn: 82821

which have no defs anywhere in the function. In particular, this fixes sinking
of instructions that reference RIP on x86-64, which is currently being modeled
as a register.

llvm-svn: 82815

llvm-svn: 82812

and skipping the defs.

llvm-svn: 82811

llvm-svn: 82803

 - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794

naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790