warning. 

llvm-svn: 137378

llvm-svn: 137375

llvm-svn: 137372

llvm-svn: 137371

llvm-svn: 137370

llvm-svn: 137368

llvm-svn: 137367

llvm-svn: 137364

llvm-svn: 137363

inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362

llvm-svn: 137359

llvm-svn: 137356

collectInterferingVRegs will be the primary function for interference
checks.

llvm-svn: 137354

llvm-svn: 137353

llvm-svn: 137352

llvm-svn: 137351

No clients are iterating over interference overlaps.

llvm-svn: 137350

llvm-svn: 137347

The InterferenceResult iterator turned out to be less important than we
thought it would be.  LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.

llvm-svn: 137346

llvm-svn: 137345

llvm-svn: 137344

llvm-svn: 137342

ancestor loops.

I have a unit test that depends on scev-unroll, which unfortunately
isn't checked in. But I will check it in when I can.

llvm-svn: 137341

llvm-svn: 137340

llvm-svn: 137339

llvm-svn: 137337

llvm-svn: 137331

llvm-svn: 137325

llvm-svn: 137324

llvm-svn: 137323

Correct immediate range for shifter operands.  Patch by James Molloy, with additional encoding fixes added by me.

llvm-svn: 137322

llvm-svn: 137321

llvm-svn: 137320

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318

llvm-svn: 137317

Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316

llvm-svn: 137313

lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion. 

llvm-svn: 137310

(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308

It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303