list multiple times when MorphNodeTo can't be applied.

llvm-svn: 99735

Type::destroy(), so it got skipped for FunctionTypes, StructTypes, and
UnionTypes.  This fixes the resulting leaks in test/Feature/opaquetypes.ll and
test/Integer/opaquetypes_bt.ll.

llvm-svn: 99732

issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.

llvm-svn: 99728

same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.

llvm-svn: 99727

from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.

llvm-svn: 99726

results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.

llvm-svn: 99725

scope due to obviously false predicate.

llvm-svn: 99723

the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.

llvm-svn: 99722

llvm-svn: 99721

llvm-svn: 99719

and initialized separately.

llvm-svn: 99717

llvm-svn: 99716

llvm-svn: 99715

llvm-svn: 99714

pointer.  There was also a SmallPtrSet whose settiness wasn't being used, so I
changed it to a SmallVector.

llvm-svn: 99713

llvm-svn: 99711

MemoizedResultChart.

llvm-svn: 99710

llvm-svn: 99707

freeing that memory when the GV is destroyed.

llvm-svn: 99706

llvm-svn: 99705

llvm-svn: 99704

llvm-svn: 99703

llvm-svn: 99700

of the previous load - it's usually important.  For example, we don't want
to blindly turn an unaligned load into an aligned one.

llvm-svn: 99699

llvm-svn: 99697

llvm-svn: 99695

converted, then use the initializer, since using the name itself won't work.

llvm-svn: 99692

it as the format for the appropriate N3V*SL*<> classes.  These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.

Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):

	vmlal.s32	q3, d2, d10[0]

llvm-svn: 99690

llvm-svn: 99686

llvm-svn: 99685

through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.

llvm-svn: 99678

Kees van Reeuwijk for PR6704

llvm-svn: 99677

to now take a format argument.  N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.

llvm-svn: 99676

'invoke' instruction. You will get a situation like this:

bb:
  %ehptr = eh.exception()
  %sel = eh.selector(%ehptr, @per, 0);

...

bb2:
  invoke _Unwind_Resume_or_Rethrow(%ehptr) %normal unwind to %lpad

lpad:
  ...

The unwinder will see the %sel call as a clean-up and, if it doesn't have a
catch further up the call stack, it will skip running it. But there *is* another
catch up the stack -- the catch for the %lpad. However, we can't see that. This
is fixed in code-gen, where we detect this situation, and convert the "clean-up"
selector call into a "catch-all" selector call. This gives us the correct
semantics.

llvm-svn: 99671

to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

llvm-svn: 99659

in the header.  How can both clang and gcc accept this?

PR6703

llvm-svn: 99658

llvm-svn: 99656

follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

llvm-svn: 99655

llvm-svn: 99646

llvm-svn: 99644