displacement values.

llvm-svn: 95773

throughout the X86 encoder.

llvm-svn: 95771

even for the immediate case.  No functionality change.

llvm-svn: 95770

MCInst it came from.

llvm-svn: 95767

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

prefix which is part of the opcode encoding.

llvm-svn: 95729

Enhance the x86 backend to show the hex values of immediates in
comments when they are large.  For example:

        movl    $1072693248, 4(%esp)    ## imm = 0x3FF00000

llvm-svn: 95728

TableGen fragment refactoring.

Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727

A8.6.279

llvm-svn: 95713

llvm-svn: 95709

llvm-svn: 95708

A8.6.335 & A8.6.336

llvm-svn: 95703

llvm-svn: 95699

in X86-32 mode.  This is still required in x86-64 mode to avoid
forming [disp+rip] encoding.  Rewrite the SIB byte decision logic
to be actually understandable.

llvm-svn: 95693

a confusing idiom to check for ESP or RSP.

llvm-svn: 95690

llvm-svn: 95689

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

For disassembly only.

A8.6.300

llvm-svn: 95669

llvm-svn: 95650

llvm-svn: 95649

llvm-svn: 95634

llvm-svn: 95627

llvm-svn: 95624

llvm-svn: 95609

llvm-svn: 95603

 2 files changed, 48 insertions(+), 83 deletions(-)

llvm-svn: 95599

backend to use X86MCTargetExpr, simplifying a bunch of code.

llvm-svn: 95595

for register tokens.  Before, if it encountered
'%al,' it would report 'al,' as the token.  Now it
correctly reports '%al'.

llvm-svn: 95594

llvm-svn: 95593

representing @GOT and friends.  Use it for
personality references as a first use.

llvm-svn: 95588

The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584

its current purpose.

llvm-svn: 95564

llvm-svn: 95560

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548

Thanks to Kristaps Straupe for noticing the bug.

llvm-svn: 95537

llvm-svn: 95506

- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.

llvm-svn: 95500

only run for x86 with fastisel. I've found it being very effective in
eliminating some obvious dead code as result of formal parameter lowering
especially when tail call optimization eliminated the need for some of the loads
from fixed frame objects. It also shrinks a number of the tests. A couple of
tests no longer make sense and are now eliminated.

llvm-svn: 95493

llvm-svn: 95477