llvm-svn: 199316

llvm-svn: 199315

llvm-svn: 194569

llvm-svn: 194205

llvm-svn: 193992

llvm-svn: 193623

This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483

llvm-svn: 190746

llvm-svn: 190745

llvm-svn: 190744

This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.

llvm-svn: 190154

This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.

llvm-svn: 190152

This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.

llvm-svn: 190148

llvm-svn: 190144

Also, fix predicates.

llvm-svn: 189432

 - Instead of setting the suffixes in a bunch of places, just set one master
   list in the top-level config. We now only modify the suffix list in a few
   suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py).

 - Aside from removing the need for a bunch of lit.local.cfg files, this enables
   4 tests that were inadvertently being skipped (one in
   Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and
   CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been
   XFAILED).

 - This commit also fixes a bunch of config files to use config.root instead of
   older copy-pasted code.

llvm-svn: 188513

register operands.

llvm-svn: 187242

operands.

llvm-svn: 187238

instructions "beqz", "bnez" and "move", when possible.

beq $2, $zero, $L1 => beqz $2, $L1
bne $2, $zero, $L1 => bnez $2, $L1
or  $2, $3, $zero  => move $2, $3

llvm-svn: 187229

Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373

function to lookup the proper tablegen'ed register enumeration.  Previously,
it was using the encoded value directly.

llvm-svn: 185026

llvm-svn: 179739

llvm-svn: 179494

but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172685

llvm-svn: 172594

Hope you are feeling better.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172579

llvm-svn: 167968

llvm-svn: 167326

Patch by Vladimir Medic.

llvm-svn: 160143

Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.

llvm-svn: 159953

llvm-svn: 159854

Include file MipsGenRegisterInfo.inc.

llvm-svn: 159851

llvm-svn: 158855

that are generated by TableGen and are already available in
MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen.

Also, fix bug in function DecodeAFGR64RegisterClass.

Patch by Vladimir Medic. 

llvm-svn: 158846

llvm-svn: 157725

Patch by Vladimir Medic. 

llvm-svn: 154935

llvm-svn: 153926

llvm-svn: 153925

Patch by Vladimir Medic.

llvm-svn: 153924