llvm-svn: 160898

llvm-svn: 160897

into predecessor blocks to enable tail call optimization.

rdar://11958338

llvm-svn: 160894

A value number is a PHI def if and only if it begins at a block
boundary. This can be derived from the def slot, a separate flag is not
necessary.

llvm-svn: 160893

This option replaces the existing live interval computation with one
based on LiveRangeCalc.cpp. The new algorithm does not depend on
LiveVariables, and it can be run at any time, before or after leaving
SSA form.

llvm-svn: 160892

llvm-svn: 160889

Patch by Tyler Nowicki!

llvm-svn: 160888

llvm-svn: 160880

llvm-svn: 160876

This can happen as long as the instruction is not reachable. Instcombine does generate these unreachable malformed selects when doing RAUW

llvm-svn: 160874

llvm-svn: 160873

Move some functions from MCRegisterInfo.h that don't need to be inline.

This shrinks llc by 8K.

llvm-svn: 160865

replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.

llvm-svn: 160841

llvm-svn: 160835

llvm-svn: 160833

I'll remove these two sub-register indexes shortly.

llvm-svn: 160831

The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but
copyPhysReg does the right thing with it. (The old pattern would
eventually produce the same cross-class copy).

llvm-svn: 160830

llvm-svn: 160823

This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns,
simplifying the emitted code a bit.

llvm-svn: 160820

The SUBREG_TO_REG instruction has magic semantics asserting that the
source value was defined by an instruction that cleared the high half of
the register. Those semantics are never actually exploited for xmm
registers.

llvm-svn: 160818

These idempotent sub-register indices don't do anything --- They simply
map XMM registers to themselves.  They no longer affect register classes
either since the SubRegClasses field has been removed from Target.td.

This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns
with COPY_TO_REGCLASS patterns which simply become COPY instructions.

The number of IMPLICIT_DEF instructions before register allocation is
reduced, and that is the cause of the test case changes.

llvm-svn: 160816

Add support for v16i32/v16i64 into the code generator. This is required for backends that use i32/i64 vectors for the getSetCCResultType function.

llvm-svn: 160814

Function names should be camel case, and start with a lower case letter.  No
functional change intended.

llvm-svn: 160813

llvm-svn: 160798

This is still a work in progress.

Out-of-order CPUs usually execute instructions from multiple basic
blocks simultaneously, so it is necessary to look at longer traces when
estimating the performance effects of code transformations.

The MachineTraceMetrics analysis will pick a typical trace through a
given basic block and provide performance metrics for the trace. Metrics
will include:

- Instruction count through the trace.
- Issue count per functional unit.
- Critical path length, and per-instruction 'slack'.

These metrics can be used to determine the performance limiting factor
when executing the trace, and how it will be affected by a code
transformation.

Initially, this will be used by the early if-conversion pass.

llvm-svn: 160796

llvm-svn: 160791

Thanks Eli for noticing.

llvm-svn: 160787

is a temporary measure until my fix for PR13021 is ready.

llvm-svn: 160778

llvm-svn: 160775

Patch by Reed Kotler.

llvm-svn: 160774

encounter an invoke of an allocation function. This should fix the dragonegg
bootstrap. Testcase to follow, later.

llvm-svn: 160757

Beckham <verena@codeplay.com>.  Reviewed by Jim Grosbach.

llvm-svn: 160753

original commit msg:
MemoryBuiltins: add support to determine the size of strdup'ed non-constant strings

llvm-svn: 160751

It is redundant; RegisterCoalescer will do the remat if it can't eliminate
the copy. Collected instruction counts before and after this. A few extra
instructions are generated due to spilling but it is normal to see these kinds
of changes with almost any small codegen change, according to Jakob.

This also fixed rdar://11830760 where xor is expected instead of movi0.

llvm-svn: 160749

Report/patch inspiration by Olaf Krzikalla.

llvm-svn: 160744

llvm-svn: 160742

llvm-svn: 160741

When a live range splits into multiple connected components, we would
arbitrarily assign <undef> uses to component 0. This is wrong when the
use is tied to a def that gets assigned to a different component:

  %vreg69<def> = ADD8ri %vreg68<undef>, 1

The use and def must get the same virtual register.

Fix this by assigning <undef> uses to the same component as the value
defined by the instruction, if any:

  %vreg69<def> = ADD8ri %vreg69<undef>, 1

This fixes PR13402. The PR has a test case which I am not including
because it is unlikely to keep exposing this behavior in the future.

llvm-svn: 160739

Before accessing a node as a ConstandSDNode, make sure it actually is one.
No testcase of non-trivial size.

rdar://11948669

llvm-svn: 160735

Include <undef> operands and virtual registers after leaving SSA form.

llvm-svn: 160734