[Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use DelaySlotFiller to fill the delay slot instead.

llvm-svn: 192160

llvm-svn: 192130

from struct byval to registers.

We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.

The fix is to pass the alignment of the struct byval.

rdar://problem/15144402

llvm-svn: 192126

llvm-svn: 192125

llvm-svn: 192124

Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

llvm-svn: 192123

llvm-svn: 192122

accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119

llvm-svn: 192111

SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107

They haven't been used for a long time. Patch by MathOnNapkins.

llvm-svn: 192099

The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.

rdar://problem/15144406

llvm-svn: 192097

Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead.

llvm-svn: 192090

llvm-svn: 192089

Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.

This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.

llvm-svn: 192088

llvm-svn: 192086

Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

llvm-svn: 192064

Fixed load folding in VPERM2I instruction.

llvm-svn: 192063

llvm-svn: 192056

in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055

This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.

llvm-svn: 192054

addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053

llvm-svn: 192046

are directly tied to the flag names in clang with no remapping in between?

llvm-svn: 192044

llvm-svn: 192040

llvm-svn: 192039

llvm-svn: 192037

When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

llvm-svn: 192035

llvm-svn: 192028

llvm-svn: 192023

llvm-svn: 192015

llvm-svn: 192006

llvm-svn: 191993

llvm-svn: 191992

llvm-svn: 191986

This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.

Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".

To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).

This patch will allow other targets the same functionality.

Jack

llvm-svn: 191982

instructions in delay slots along with the original branch instructions.

llvm-svn: 191978

optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

llvm-svn: 191963

The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

llvm-svn: 191962

Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

llvm-svn: 191961