- Instead of embedding 'lock' into each mnemonic of atomic
  instructions except 'xchg', we teach X86 assembly printer to output 'lock'
  prefix similar to or consistent with code emitter.

llvm-svn: 164659

llvm-svn: 164642

llvm-svn: 164640

Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

llvm-svn: 164628

- Turn on atomic6432.ll and add specific test case as well

llvm-svn: 164616

When a BL/BLX references a symbol in the same translation unit that is
out of range, use an external relocation. The linker will use this to
generate a branch island rather than a direct reference, allowing the
relocation to resolve correctly.

rdar://12359919

llvm-svn: 164615

llvm-svn: 164611

Fix an illegal tailcall opt where the callee returns a double via xmm while caller returns x86_fp80 via st0. rdar://12229511

llvm-svn: 164588

rdar://9795790

llvm-svn: 164577

Even out-of-line jump tables can be in the code section, so mark them
as data-regions for those targets which support the directives.

rdar://12362871&12362974

llvm-svn: 164571

Also remove an unused argument.

llvm-svn: 164567

store when handling byval arguments. Thus preventing reordering of the store
with load with post-RA scheduler.

llvm-svn: 164553

llvm-svn: 164548

llvm-svn: 164459

llvm-svn: 164458

As before with load instructions, oddities like "asr #32", "rrx" could
be printed incorrectly.

Patch by Chris Lidbury.

llvm-svn: 164456

This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.

Patch by Chris Lidbury.

llvm-svn: 164455

llvm-svn: 164453

llvm-svn: 164452

llvm-svn: 164435

llvm-svn: 164434

TargetLowering's callback functions.

llvm-svn: 164431

llvm-svn: 164430

llvm-svn: 164429

llvm-svn: 164428

llvm-svn: 164420

llvm-svn: 164415

llvm-svn: 164414

non-aligned i32 loads/stores.
rdar://12304911

llvm-svn: 164381

llvm-svn: 164372

Make the 'get*AlignmentFromAttr' functions into member functions within the Attributes class. Now with fix.

llvm-svn: 164370

Quick review against the manual revealed a few obvious mistakes.

llvm-svn: 164361

- Fix PR5145 and turn on test 8-bit atomic ops

llvm-svn: 164358

- Rewirte most atomic instructions in templates for both better
  maintenance and future extensions, such as HLE in TSX.

llvm-svn: 164357

llvm-svn: 164354

Patch by Reed Kotler.

llvm-svn: 164349

non-halfword-aligned i16 loads/stores.
rdar://12304911

llvm-svn: 164345

llvm-svn: 164344

llvm-svn: 164343

The expression based expansion too often results in IR level optimizations
splitting the intermediate values into separate basic blocks, preventing
the formation of the VBSL instruction as the code author intended. In
particular, LICM would often hoist part of the computation out of a loop.

rdar://11011471

llvm-svn: 164340