It is still possible to if-convert if the tail block has extra
predecessors, but the tail phis must be rewritten instead of being
removed.

llvm-svn: 161781

This was causing unnecessary spills/restores of callee saved registers.

Fixes PR13572.

Patch by Pranav Bhandarkar!

llvm-svn: 161778

llvm-svn: 161777

Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ISDNode has more than one user. 

rdar://11876519

llvm-svn: 161775

OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed
to a memory operand.

PR13576

llvm-svn: 161769

Patch by Weiming Zhao.

llvm-svn: 161768

Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6.

llvm-svn: 161763

llvm-svn: 161758

[asan] remove the code for --asan-merge-callbacks as it appears to be a bad idea. (partly related to Bug 13225)

llvm-svn: 161757

llvm-svn: 161751

llvm-svn: 161750

Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit
accesses being selected, so we need to use an appropriate width load in those
cases.

llvm-svn: 161748

Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and putting an a couple if conditions in a better order.

llvm-svn: 161746

llvm-svn: 161745

llvm-svn: 161743

Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result.

llvm-svn: 161742

llvm-svn: 161740

of the range. Fixes PR13581!

llvm-svn: 161739

llvm-svn: 161738

Remove unnecessary call to setOperationAction for SETCC of v2i64 under SSE42. It was already called for the same under SSE2.

llvm-svn: 161737

architecture

It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7
thumb O3.

llvm-svn: 161736

llvm-svn: 161735

llvm-svn: 161734

Use MVT.isXBitVector instead of EVT.isXBitVector when setting up operation actions. Compiles to smaller code.

llvm-svn: 161733

- FCMOV only supports a subset of X86 conditions. Skip boolean
  simplification if X86 condition is not valid for FCMOV.
- add a minimal test case for PR13577.

llvm-svn: 161732

Create isXBitVector methods in MVT and call them from EVT. This allows targets to call them with an MVT without needing to convert to EVT.

llvm-svn: 161731

Move setOperationAction for CONCAT_VECTORS for 256-bit vectors into loop since all 256-bit types are supported.

llvm-svn: 161730

llvm-svn: 161729

This is common e.g. when doing rip-relative addressing on x86_64.

llvm-svn: 161728

llvm-svn: 161727

llvm-svn: 161726

Add a couple default: llvm_unreachable() to some switch statements. Fix a bad message in an existing llvm_unreachable.

llvm-svn: 161725

FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge.

FeatureFastUAMem is already on if we pass in nehalem or westmere as a command
argument.

rdar: 7252306
llvm-svn: 161717

Detect when there is not enough available ILP, so if-conversion can't
speculate instructions for free.

Compute the lengthening of the critical path when inserting a select
instruction that depends on the condition as well as both sides of the
if.

Reject conversions that would stretch the critical path by more than
half a mispredict penalty.

llvm-svn: 161713

llvm-svn: 161712

Trace::getResourceLength() computes the number of cycles required to
execute the trace when ignoring data dependencies. The number can be
compared to the critical path to estimate the trace ILP.

Trace::getPHIDepth() computes the data dependency depth of a PHI in a
trace successor that isn't necessarily part of the trace.

llvm-svn: 161711

landingpad.  Enforce it in the verifier, and fix the regression tests to match.

llvm-svn: 161697

This change is to be enabled in clang.

rdar://9877866
PR://13350

llvm-svn: 161693

They identify the PHI predecessors in both diamonds and triangles.

llvm-svn: 161689

When a trace ends with a back-edge, include PHIs in the loop header in
the height computations. This makes the critical path through a loop
more accurate by including the latencies of the last instructions in the
loop.

llvm-svn: 161688