to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903

llvm-svn: 98902

llvm-svn: 98901

llvm-svn: 98889

llvm-svn: 98888

Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.

llvm-svn: 98887

llvm-svn: 98881

were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880

llvm-svn: 98869

llvm-svn: 98866

llvm-svn: 98864

llvm-svn: 98862

No functional changes.

llvm-svn: 98860

temporary workaround for matching inc/dec on x86_64 to the correct instruction.
 - This hack will eventually be replaced with a robust mechanism for handling
   matching instructions based on the available target features.

llvm-svn: 98858

llvm-svn: 98855

llvm-svn: 98853

RecyclingAllocator to allow client code to be simpler, and
simplify several clients.

llvm-svn: 98847

always create a new jump table.  The intention was to avoid merging jump
tables in SelectionDAGBuilder, and to wait for the branch folding pass to
merge tables.  Unfortunately, the same getJumpTableIndex() method is also
used to merge tables in branch folding, so as a result of this change
branch tables are never merged.  Worse, the branch folding code is expecting
getJumpTableIndex to always return the index of an existing table, but with
this change, it never does so.  In at least some cases, e.g., pr6543, this
creates references to non-existent tables.

I've fixed the problem by adding a new createJumpTableIndex function, which
will always create a new table, and I've changed getJumpTableIndex to only
look at existing tables.

llvm-svn: 98845

files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839

llvm-svn: 98838

llvm-svn: 98835

intrinsics.  The intrinsic lookup code assumes that this check has been done
and assumes the names are at least 6 characters long.  Valgrind complained
about this.  pr6638.

llvm-svn: 98831

llvm-svn: 98830

BumpPtrAllocator-allocated region to allow it to be stored in a more
compact form and to avoid the need for a non-trivial destructor call.

Use this new mechanism in ScalarEvolution instead of
FastFoldingSetNode to avoid leaking memory in the case where a
FoldingSetNodeID uses heap storage, and to reduce overall memory
usage.

llvm-svn: 98829

llvm-svn: 98819

llvm-svn: 98810

llvm-svn: 98793

MCValue: Change to holding MCSymbolRefExprs instead of MCSymbols, we will need this for accessing to symbol modifiers.

llvm-svn: 98791

MC/Darwin: Add a new target hook for whether the target uses "reliable" symbol differences, basically whether the assembler should attempt to understand atoms when using scattered symbols.

Also, avoid some virtual call overhead.

llvm-svn: 98789

This reverts commit 98776. It broke the llvm-gcc boot strap.

llvm-svn: 98784

X86 address mode matching code MatchAddressRecursively does some aggressive hack which require doing a RAUW. It may end up deleting some SDNode up stream. It should avoid referencing deleted nodes.

llvm-svn: 98780

llvm-svn: 98778

There is a better way coming up.

llvm-svn: 98777

Remove ugly hack that aborted the coalescer before using N^2 time.

This affects functions with very complicated live intervals for physical
registers, i.e. functions with thousands of function calls.

llvm-svn: 98776

matches that of Firstcond[0] and E means otherwise.  The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing.  The disassembler also depends
on this arrangement.  This is similar to what's described in A2.5.2 ITSTATE.

Ran:

utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2

successfully.

llvm-svn: 98775

addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>.

This patch removes the impl of printT2AddrModeImm8s4OffsetOperand() from
ARMAsmPrinter.cpp.  It is used by disassembler as of now.

llvm-svn: 98774

llvm-svn: 98769

in svn r74988 but the format field was never widened.

llvm-svn: 98768

llvm-svn: 98763

llvm-svn: 98762