When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.

This makes the fast allocator independent of incoming kill flags.

llvm-svn: 103866

return value optimization. Sema marks return statements with their
NRVO candidates (which may or may not end up using the NRVO), then, at
the end of a function body, computes and marks those variables that
can be allocated into the return slot.

I've checked this locally with some debugging statements (not
committed), but there won't be any tests until CodeGen comes along.

llvm-svn: 103865

implicit conversions where needed.  This fixes an error reported
on cfe-dev, not really worth a testcase though.

llvm-svn: 103864

inliner did in r103653. Why does the always inliner even bother with cost
estimates anyways?

llvm-svn: 103858

llvm-svn: 103857

llvm-svn: 103856

llvm-svn: 103855

allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854

llvm-svn: 103852

llvm-svn: 103851

llvm-svn: 103850

"return" statement and mark the corresponding CXXConstructExpr as
elidable. Teach CodeGen that eliding a temporary is different from
eliding an object construction.

This is just a baby step toward NRVO.

llvm-svn: 103849

llvm-svn: 103843

llvm-svn: 103842

llvm-svn: 103837

instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.

llvm-svn: 103835

llvm-svn: 103834

llvm-svn: 103833

setting kill flags.

llvm-svn: 103832

llvm-svn: 103831

llvm-svn: 103830

replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)

llvm-svn: 103829

llvm-svn: 103828

llvm-svn: 103827

llvm-svn: 103826

assembler defaults to on.

llvm-svn: 103825

of "has calls". That's probably wrong, but it needs further
investigation. Revert to the original behavior until this is settled.

llvm-svn: 103824

llvm-svn: 103823

llvm-svn: 103822

llvm-svn: 103821

llvm-svn: 103820

llvm-svn: 103819

llvm-svn: 103814

stack.

llvm-svn: 103813

Radar 7923673.

llvm-svn: 103812

part (or possibly all) of PR7132.

llvm-svn: 103810

Clang's representation of the C type system to clients.  It is nowhere near complete, and will
be expanded on demand.

llvm-svn: 103809

llvm-svn: 103808

llvm-svn: 103807

llvm-svn: 103806