Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.

llvm-svn: 140954

Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.

llvm-svn: 139691

llvm-svn: 139690

Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.

llvm-svn: 139588

Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.

llvm-svn: 139486

llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028

Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.

llvm-svn: 138997

Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

llvm-svn: 138623

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552

Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.

llvm-svn: 138551

llvm-svn: 138034

VEX prefixes are working for triadic AVX
instructions.  This concludes the patch set to
enable AVX support for the X86 disassebler.

llvm-svn: 127647

llvm-svn: 119050

weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084

llvm-svn: 115580

disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.

llvm-svn: 108226

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

llvm-svn: 101642

for the encoding and is not the same as vmptrld.

llvm-svn: 97992

llvm-svn: 96076

fix swapgs to be spelled right.

llvm-svn: 96058

llvm-svn: 96045

llvm-svn: 91900

data on them, for example:

	addb	%al, (%rax)
simple-tests.txt:11:5: error: excess data detected in input
0 0 0 0 0 
    ^

llvm-svn: 91896

comments.  Also, check in a simple testcase for the disassembler,
including a test for r91864

llvm-svn: 91894