llvm-svn: 48762

and uninitialized values passed-by-value as arguments to message expressions.

llvm-svn: 48760

llvm-svn: 48759

llvm-svn: 48758

llvm-svn: 48757

llvm-svn: 48756

llvm-svn: 48755

for message bubbles.

llvm-svn: 48754

llvm-svn: 48753

If the coalescer commuted a def MI to allow coalescing, it can changed a previously coalesced copy into an non-identity copy.

llvm-svn: 48752

llvm-svn: 48751

mask.

llvm-svn: 48750

llvm-svn: 48749

llvm-svn: 48748

llvm-svn: 48747

- SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction.

llvm-svn: 48746

llvm-svn: 48745

llvm-svn: 48744

llvm-svn: 48743

llvm-svn: 48742

llvm-svn: 48741

llvm-svn: 48740

llvm-svn: 48739

llvm-svn: 48738

llvm-svn: 48736

llvm-svn: 48734

llvm-svn: 48733

llvm-svn: 48732

llvm-svn: 48731

llvm-svn: 48730

llvm-svn: 48729

llvm-svn: 48728

field to store the alignment value instead of haing a
separate field.

llvm-svn: 48727

llvm-svn: 48726

Increasing the inline limit from (overly conservative) 200 to 300. Given each BB costs 20 and each instruction costs 5, 200 means a 4 BB function + 24 instructions (actually less because caller's size also contributes to it).

Furthermore, double the limit when more than 10% of the callee instructions are vector instructions. Multimedia kernels tend to love inlining.

llvm-svn: 48725

llvm-svn: 48723

llvm-svn: 48722

llvm-svn: 48721

llvm-svn: 48720

With this pass, StrongPHIElim can compile very simple testcases correctly.  There's still a ways
to go before it's ready for prime time, though.

llvm-svn: 48719