rip-relative addresses, and add a testcase.

llvm-svn: 96040

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

llvm-svn: 95827

with some of the recent changes that have gone into llvm-mc.

llvm-svn: 95826

x86_32-encoding.s in on expectation of it passing.

llvm-svn: 95806

llvm-svn: 95804

containing the subset of the full auto generated test case that currently
encodes correctly.  Again it is useful as we bring up the the new encoder
to make sure currently working stuff stays working.

llvm-svn: 95791

prefix which is part of the opcode encoding.

llvm-svn: 95729

in X86-32 mode.  This is still required in x86-64 mode to avoid
forming [disp+rip] encoding.  Rewrite the SIB byte decision logic
to be actually understandable.

llvm-svn: 95693

llvm-svn: 95634

llvm-svn: 95448

redundant with a correct one) pattern that was added for the disassembler.

llvm-svn: 95446

llvm-svn: 95444

Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.

llvm-svn: 95252

some mechanism for specifying alternative syntaxes, but I'm not sure what form
that should take yet.

llvm-svn: 95158

It's unclear if the matcher is nondeterminstic of what here,
but I'm getting matches without TAILCALL and some other hosts
are getting matches with it.

llvm-svn: 95149

instructions exactly like 'as', and produce equivalent .o files.

llvm-svn: 95143

llvm-svn: 95135

llvm-svn: 95122

llvm-svn: 95120

This test case is different subset of the full auto generated test case, and a
larger subset that is in x86_32-bit.s (that set will encode correctly).  These
instructions can pass though llvm-mc as it were a logical cat(1) and then
reassemble to the same instruction.  It is useful as we bring up the parser and
matcher so we don't break things that currently work.

llvm-svn: 95107

something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
  movl $0, %eax
as
  movl 0, %eax
Feel free to guess how well that worked.

llvm-svn: 94869

 - This test case is auto generated, and has been verified to round-trip
   correctly through llvm-mc by checking the assembled .o file before and after
   piping through llvm-mc. It will be extended over time as the matcher grows
   support for more instructions.

llvm-svn: 94857

llvm-svn: 94438

movw	$8, (_cost_table_-L97$pb)+66(%eax)

After the parens, we could still have a binop.

llvm-svn: 94345

llvm-svn: 94259

llvm-svn: 94205

emits one directive instead of N.  Not doing this would be a
significant regression on the # bytes generated by .fill.

llvm-svn: 93889

llvm-svn: 93866

llvm-svn: 91900

data on them, for example:

	addb	%al, (%rax)
simple-tests.txt:11:5: error: excess data detected in input
0 0 0 0 0 
    ^

llvm-svn: 91896

comments.  Also, check in a simple testcase for the disassembler,
including a test for r91864

llvm-svn: 91894

llvm-svn: 84257

variables and symbols invalid.

llvm-svn: 84232

since they are allowed to be redefined.

llvm-svn: 84230

that a symbol stub section with no attributes can be parsed as in:
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16

llvm-svn: 83488

run if appropriate target is supported.

llvm-svn: 82419

transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1"

llvm-svn: 82385

parses the .word directive as 4 bytes and ARMAsmParser::ParseInstruction will
give an error is called.  Broke out the test of the .word directive into two
different test cases, one for x86 and one for arm.

llvm-svn: 81817

llvm-svn: 81724