llvm-svn: 83254

a new class, MachineInstrIndex, which hides arithmetic details from
most clients. This is a step towards allowing the register allocator
to update/insert code during allocation.

llvm-svn: 81040

llvm-svn: 79766

as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.

A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test 
condition has been updated to reflect this.

llvm-svn: 75097

llvm-svn: 74114

llvm-svn: 73750

llvm-svn: 73634

llvm-svn: 72729

llvm-svn: 72030

llvm-svn: 71057

This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.

llvm-svn: 69743

register is available and when it's profitable.

e.g.
     xorq  %r12<kill>, %r13
     addq  %rax, -184(%rbp)
     addq  %r13, -184(%rbp)
==>
     xorq  %r12<kill>, %r13
     movq  -184(%rbp), %r12
     addq  %rax, %r12
     addq  %r13, %r12
     movq  %r12, -184(%rbp)

Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.

llvm-svn: 69341

the subreg field to 0, since the subreg field is only used
for virtual register subregs. This doesn't change
current functionality; it just eliminates bogus noise from
debug output.

llvm-svn: 68955

register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

llvm-svn: 68099

llvm-svn: 68092

llvm-svn: 68059

llvm-svn: 67372

llvm-svn: 67335

Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded.

llvm-svn: 67068

llvm-svn: 67000

llvm-svn: 66780

Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files.  No (intended) functionality change.

llvm-svn: 66720

Yet another case where the spiller marked two uses of the same register on the same instruction as kill. This fixes PR3706.

llvm-svn: 66428

llvm-svn: 66363

llvm-svn: 65679

llvm-svn: 65498

If an available register falls through to a succ block, unset the last kill. Sorry, it's impossible to reduce a sensible test case. It basically requires the moon and stars to align in order to cause a failure.

llvm-svn: 65497

A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes.

llvm-svn: 64745

llvm-svn: 64428

the new way, where all of the information is passed on SDNodes and machine
instructions.

llvm-svn: 64427

llvm-svn: 64381

It's (currently) not safe to keep certain physical registers live across basic blocks, e.g. x86 fp stack registers.

llvm-svn: 64374

If availability info is kept when fallthrough into a bb, add the available registers to live-in set.

llvm-svn: 64372

Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction.

llvm-svn: 64339

Implement PR3495: local spiller optimization. The local spiller can now keep availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies.

llvm-svn: 64298

llvm-svn: 63599

llvm-svn: 62600

llvm-svn: 60392

Patch by Lang Hames!

llvm-svn: 57720