use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346

Fixed a bug in the coalescer where intervals were occasionally merged despite a real interference. This fixes rdar://problem/7157961.

llvm-svn: 85338

llvm-svn: 85325

llvm-svn: 85323

Do not held on to DenseMap slot accross map insertion. The insertion may cause the map to grow rending the slot invalid.
Use this opportunity to use ValueMap instead of DenseMap.

llvm-svn: 85298

llvm-svn: 85296

Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.

llvm-svn: 85281

(assembler,asmprinter, bc reader+writer) and document it.  Codegen
currently aborts on it.

llvm-svn: 85274

thread safe either.

llvm-svn: 85253

do anything than return "I don't know" at the moment.

llvm-svn: 85189

Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176

Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.

llvm-svn: 85166

llvm-svn: 85146

Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.

llvm-svn: 85145

machineinstr whether the aliased register is dead, rather than the original
register is dead. This allows it to get the correct answer when examining
an instruction like this:
  CALLpcrel32 <ga:foo>, %AL<imp-def>, %EAX<imp-def,dead>
where EAX is dead but a subregister of it is still live. This fixes PR5294.

llvm-svn: 85135

llvm-svn: 85127

  bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091

direct inclusion edge from System to Support.

llvm-svn: 85086

llvm-svn: 85047

llvm-svn: 85046

Do not delete identity insert_subreg even if dest is virtual. Let later passes delete them. This avoids register scavenger complain.

llvm-svn: 85045

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

spill, it should avoid doing so inside the live range of a virtual register.

llvm-svn: 85026

used elsewhere - an exit block is a block outside the loop branched to
from within the loop. An exiting block is a block inside the loop that
branches out.

llvm-svn: 85019

llvm-svn: 84983

llvm-svn: 84978

the scale overflows pointer-sized arithmetic. This fixes PR5281.

llvm-svn: 84954

does.

llvm-svn: 84916

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

llvm-svn: 84911

llvm-svn: 84894

llvm-svn: 84806

to break up CFG diamonds by banishing one of the blocks to the end of
the function, which is bad for code density and branch size.

This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the
benchmark cited as the reason for the change, however I've examined
the code and it looks more like a case of gaming a particular
branch than of being generally applicable.

llvm-svn: 84803

llvm-svn: 84792

handles T2 and ARM use cases.

llvm-svn: 84761

llvm-svn: 84749

llvm-svn: 84727

Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.

llvm-svn: 84691

transform.

llvm-svn: 84683

llvm-svn: 84682