llvm-svn: 24064

llvm-svn: 24051

llvm-svn: 24018

llvm-svn: 24017

llvm-svn: 24016

llvm-svn: 24013

llvm-svn: 24012

llvm-svn: 23994

machine.  This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.

llvm-svn: 23993

llvm-svn: 23991

llvm-svn: 23988

llvm-svn: 23987

llvm-svn: 23986

llvm-svn: 23985

llvm-svn: 23984

llvm-svn: 23982

if the dag combiner isn't run

llvm-svn: 23981

CPU.

llvm-svn: 23974

llvm-svn: 23909

llvm-svn: 23906

future.

llvm-svn: 23902

llvm-svn: 23892

to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.

llvm-svn: 23880

llvm-svn: 23878

let the generic code handle it.  This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.

also, reindent this code

llvm-svn: 23874

llvm-svn: 23870

haven't seen it fire on our testsuite.

llvm-svn: 23863

Add a new flag to TargetLowering indicating if the target has really cheap
  signed division by powers of two, make ppc use it.  This will probably go
  away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.

llvm-svn: 23853

llvm-svn: 23842

that the nodes can be folded with other nodes, and we can not duplicate
code in every backend.  Alpha will probably want this too.

llvm-svn: 23835

Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830

doing something clever.

llvm-svn: 23824

llvm-svn: 23820

llvm-svn: 23818

llvm-svn: 23813

llvm-svn: 23811

code for long long foo(long long a, long long b) { return a + b; }

_foo:
        or r2, r3, r3
        or r3, r4, r4
        or r4, r5, r5
        or r5, r6, r6
        rldicr r2, r2, 32, 31
        rldicl r3, r3, 0, 32
        rldicr r4, r4, 32, 31
        rldicl r5, r5, 0, 32
        or r2, r3, r2
        or r3, r5, r4
        add r4, r3, r2
        rldicl r2, r4, 32, 32
        or r4, r4, r4
        or r3, r2, r2
        blr

llvm-svn: 23809

llvm-svn: 23805

will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.

Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG.  Something wll have to be
figured out.

llvm-svn: 23803

allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).

llvm-svn: 23802