llvm-svn: 142741

llvm-svn: 142726

llvm-svn: 142691

llvm-svn: 142682

llvm-svn: 142675

Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670

llvm-svn: 142647

Modify the script to output the regressions and passes into categories. My Python-fu could use some improving...

llvm-svn: 142643

llvm-svn: 142640

llvm-svn: 142608

the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM.  Flavors should be independent of each other.  This
especially matters if the compiler built for the previous flavour doesn't
actually work!

llvm-svn: 142607

In fact this commit is not intended to change anything unless you
use one of the new command line flags.

llvm-svn: 142577

llvm-svn: 142559

Duncan pointed out that sometimes CC and CXX are used to specify the compiler. Also that the configure script takes care of finding an appropriate compiler if one's not specified.

llvm-svn: 142489

llvm-svn: 142486

llvm-svn: 142482

llvm-svn: 142464

llvm-svn: 142441

llvm-svn: 142369

llvm-svn: 142356

llvm-svn: 142321

llvm-svn: 142303

NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293

llvm-svn: 142282

llvm-svn: 142280

Fix unused variable warning in the rare circumstance that we have no feature-dependent instructions.

llvm-svn: 142193

Shaves 200k off Release-Asserts clang binaries on i386.

llvm-svn: 142191

llvm-svn: 142185

llvm-svn: 142173

This removes support for building llvm-gcc. It will eventually add support for
building other projects.

llvm-svn: 142165

llvm-svn: 142155

llvm-svn: 142141

llvm-svn: 142122

Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.

llvm-svn: 142117

string, pass it around as an enum.

llvm-svn: 142107

the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106

Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen

llvm-svn: 142105

llvm-svn: 142098

llvm-svn: 142097

Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.

llvm-svn: 142082