llvm-svn: 117143

llvm-svn: 117134

llvm-svn: 117133

llvm-svn: 117131

llvm-svn: 117128

llvm-svn: 117126

llvm-svn: 117121

llvm-svn: 117119

definitions.

llvm-svn: 117114

llvm-svn: 117111

llvm-svn: 117108

llvm-svn: 117099

It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087

llvm-svn: 117085

weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084

It choked BugPoint on Mingw.

llvm-svn: 117083

llvm-svn: 117080

llvm-svn: 117076

llvm-svn: 117073

llvm-svn: 117072

llvm-svn: 117070

llvm-svn: 117068

llvm-svn: 117062

X86: Base _fltused on the FunctionType of the called value instead of the potentially null "CalledFunction". Thanks Duncan!

This is needed for indirect calls.

llvm-svn: 117061

llvm-svn: 117060

llvm-svn: 117058

half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056

llvm-svn: 117055

mostly based on the ARM AsmParser at this time and is not particularly
functional.

Changed the MBlaze data layout from:
    "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
    "E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.

Cleaned up the MBlaze source code:
    1. The floating point register class has been removed. The
       MicroBlaze does not have floating point registers. Floating
       point values are simply stored in integer registers.
    2. Renaming the CPURegs register class to GPR to reflect the
       standard naming.
    3. Removing a lot of stale code from AsmPrinter after
       the conversion to InstPrinter.
    4. Simplified sign extended loads by marking them as
       expanded in ISelLowering.

llvm-svn: 117054

llvm-svn: 117053

the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051

llvm-svn: 117050

llvm-svn: 117048

llvm-svn: 117047

Parent - union(Y, ...). Doh.

llvm-svn: 117042

unconditional branch.

llvm-svn: 117041

llvm-svn: 117040

llvm-svn: 117039

from losing the variant when producing a relocation on an alias.

llvm-svn: 117037

sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031