This removes support for building llvm-gcc. It will eventually add support for
building other projects.

llvm-svn: 142165

directly manipulates the weights inside of the BranchProbabilityInfo
that is passed in.

llvm-svn: 142163

llvm-svn: 142162

llvm-svn: 142158

llvm-svn: 142155

llvm-svn: 142154

llvm-svn: 142153

Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152

llvm-svn: 142151

on the memcpy call will pull up other unrelated stuff. Fixes PR11142.

llvm-svn: 142150

The decision was to pack the bits. Currently no codegen supports this.
Currently, all of the bits in the vector are saved into the same address
in memory.

llvm-svn: 142149

llvm-svn: 142141

While at it, merge some format strings.

llvm-svn: 142140

llvm-svn: 142139

<stdin>:1:12: error: register %rax is only available in 64-bit mode
   incl    %rax
           ^~~~

llvm-svn: 142137

llvm-svn: 142136

X86AsmParser: Synthesize EndLoc for tokens out of StartLoc + Length and print ranges for invalid operands.

<stdin>:1:4: error: invalid instruction mnemonic 'abc'
   abc incl    %edi
   ^~~

llvm-svn: 142135

This reenables proper inline asm diagnostics in clang

llvm-svn: 142132

no pattern.

llvm-svn: 142130

llvm-svn: 142125

LangImpl6.html (it needed to defined the 'binary :' operator).
PR9052

llvm-svn: 142123

llvm-svn: 142122

Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.

llvm-svn: 142117

llvm-svn: 142112

These missing flags show up as errors when running -verify-coalescing on
test-suite.

llvm-svn: 142111

llvm-svn: 142110

llvm-svn: 142108

string, pass it around as an enum.

llvm-svn: 142107

the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106

Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen

llvm-svn: 142105

CMake: Introduce LLVM_CLANG_SOURCE_DIR, "tools/clang" by default. Clang will not be built if LLVM_CLANG_SOURCE_DIR="" or ${LLVM_CLANG_SOURCE_DIR}/CMakeLists.txt is not found.

llvm-svn: 142103

autoconf: Introduce --with-clang-srcdir, to build out-of-tree clang as tools/clang on tools/Makefile.

llvm-svn: 142102

llvm-svn: 142101

test/Makefile: Inspect $(PROJ_OBJ_ROOT)/tools/clang/Makefile instead of $(PROJ_SRC_ROOT)/tools/clang for "check-all".

llvm-svn: 142100

llvm-svn: 142098

llvm-svn: 142097

Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.

llvm-svn: 142089

Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.

llvm-svn: 142082

The CELL backend cannot select patterns for  vector trunc-store and shl on v2i64; CellSPU/shift_ops.ll fails when promoting elements.

llvm-svn: 142081

llvm-svn: 142080