llvm-svn: 106063

llvm-svn: 106057

Please use the fast allocator instead.

llvm-svn: 106051

llvm-svn: 106038

llvm-svn: 106027

llvm-svn: 106024

SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a
copy is coalescable, and in very rare cases it can return true where LHS is not
live - the coalescable copy can come from an alias of the physreg in LHS.

llvm-svn: 106021

llvm-svn: 106015

combined to an insert_subreg, i.e., where the destination register is larger
than the source.  We need to check that the subregs can be composed for that
case in a symmetrical way to the case when the destination is smaller.

llvm-svn: 106004

Early clobbers defining a virtual register were first alocated to a physreg and
then processed as a physreg EC, spilling the virtreg.

This fixes PR7382.

llvm-svn: 105998

Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:

- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.

CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.

The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.

llvm-svn: 105997

replacing the overly conservative checks that I had introduced recently to
deal with correctness issues.  This makes a pretty noticable difference
in our testcases where reg_sequences are used.  I've updated one test to
check that we no longer emit the unnecessary subreg moves.

llvm-svn: 105991

llvm-svn: 105987

Make sure to skip the dbg_value instructions when moving dups out of the
diamond. rdar://7797940

llvm-svn: 105965

- Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it.

llvm-svn: 105959

llvm-svn: 105955

llvm-svn: 105942

clean-up to a catch-all after inlining, take into account that there could be
filter IDs as well. The presence of filters don't mean that the selector catches
anything. It's just metadata information.

llvm-svn: 105872

llvm-svn: 105862

llvm-svn: 105861

llvm-svn: 105828

llvm-svn: 105775

This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.

llvm-svn: 105749

Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.

llvm-svn: 105745

   %reg1025 = <sext> %reg1024
    ...
   %reg1026 = SUBREG_TO_REG 0, %reg1024, 4

into this:

   %reg1025 = <sext> %reg1024
    ...
   %reg1027 = EXTRACT_SUBREG %reg1025, 4
   %reg1026 = SUBREG_TO_REG 0, %reg1027, 4

The problem here is that SUBREG_TO_REG is there to assert that an implicit zext
occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG
here, it will give us the value after the <sext>, not the original value of
%reg1024 before <sext>.

llvm-svn: 105741

llvm-svn: 105665

that it is an immediate before checking that the instruction is an
EXTRACT_SUBREG.

llvm-svn: 105585

llvm-svn: 105561

llvm-svn: 105554

llvm-svn: 105541

llvm-svn: 105511

I don't think this ever resulted in problems on x86, but it
would on ARM.

llvm-svn: 105509

llvm-svn: 105502

llvm-svn: 105498

llvm-svn: 105492

llvm-svn: 105481

register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473

replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453

Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass.  Some of
these constraints can be relaxed with a bit more work.  Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.

llvm-svn: 105437

llvm-svn: 105435