llvm-svn: 101880

comment in the generated table.

llvm-svn: 99794

where an incorrect number of operands is provided to an sdnode instead
of just a few cases.

llvm-svn: 99761

and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)

llvm-svn: 99759

transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.

llvm-svn: 99756

llvm-svn: 99747

by rotating it.

llvm-svn: 99746

llvm-svn: 99744

same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.

llvm-svn: 99727

from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.

llvm-svn: 99726

results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.

llvm-svn: 99725

llvm-svn: 99703

in some more places.

llvm-svn: 99366

instead of reimplementing it wrong and poorly.

llvm-svn: 99357

llvm-svn: 99354

llvm-svn: 99353

instead of as a single element list with VoidTy.  Now with a fix
for the verifier.

llvm-svn: 99206

llvm-svn: 99111

llvm-svn: 99011

instead of as a single element list with VoidTy.

llvm-svn: 99009

ApplyTypeConstraint) and make it handle multiple result nodes.

llvm-svn: 99003

to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.

llvm-svn: 98999

we don't blow the smallvector as often.  No functionality change.

llvm-svn: 98968

from the pattern if present, and we use it instead of the bit.

llvm-svn: 98938

dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934

llvm-svn: 98933

llvm-svn: 98927

llvm-svn: 98918

to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910

llvm-svn: 98906

llvm-svn: 98904

llvm-svn: 98900

like this:

 def : Pat<(add ...),
           (FOOINST)>;

When fooinst only has a single implicit def (e.g. to R1).  This will be handled
as if written as (set R1, (FOOINST ...))

llvm-svn: 98897

shouldn't change this.

llvm-svn: 98872

Add checking that the input/output operand list in spelled right.

llvm-svn: 98865

now enforces that input/output named values have hte same type.

llvm-svn: 98535

changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!

llvm-svn: 98534

needs to be majorly refactored, but this spot bugfix allows
things like:

 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
                             (vector_shuffle (v4i32 node:$lhs), node:$rhs), [{
...

llvm-svn: 97952

(set GPR, somecomplexpattern)

if somecomplexpattern doesn't declare what it can match.

llvm-svn: 97513

ordered correctly.  Previously it would get in trouble when
two patterns were too similar and give them nondet ordering.
We force this by using the record ID order as a fallback.

The testsuite diff is due to alpha patterns being ordered
slightly differently, the change is a semantic noop afaict:

< 	lda $0,-100($16)
---
> 	subq $16,100,$0

llvm-svn: 97509