Treat stores as reading memory, just to play safe.

llvm-svn: 56188

llvm-svn: 56184

Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183

llvm-svn: 56182

llvm-svn: 56181

llvm-svn: 56180

llvm-svn: 56179

llvm-svn: 56178

llvm-svn: 56176

llvm-svn: 56172

llvm-svn: 56171

vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165

ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162

representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161

with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159

when a readonly declaration is called, set a
flag.  This is faster and uses less memory.
In theory it is less accurate, because before
only those internal globals that were read
by someone were being marked "Ref", but now
all are.  But in practice, thanks to other
passes, all internal globals of the kind
considered here will be both read and stored
to: those only read will have been turned
into constants, and those only stored to will
have been deleted.

llvm-svn: 56143

safe in the presence of NaNs.

llvm-svn: 56136

getelementptr indices, inserting an explicit cast if necessary.
This helps expose the sign-extension operation to other optimizations.

llvm-svn: 56133

Patch by Nicolas Capens!

llvm-svn: 56129

llvm-svn: 56126

When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.

llvm-svn: 56119

Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118

llvm-svn: 56117

llvm-svn: 56116

(unless passed one via a parameter), even if they
are IntrWriteMem.

llvm-svn: 56115

cases it was still getting lucky and detecting overflow
but it was clearly incorrect.

llvm-svn: 56113

llvm-svn: 56112

variables.

llvm-svn: 56105

llvm-svn: 56097

cmp-and-swap reversed the Cmp and Swap arguments; comments
make it clear this is unintentional.  Unfortunately, the
x86 BE had a compensating reversal, which is removed here.
PPC is OK.

From inspection of the Alpha code I think it is OK, but
if somebody has that platform please check it out.  I
cannot test on that platform.

llvm-svn: 56091

If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up.  This fixes 445.gobmk on
X86-64 in fast isel.

llvm-svn: 56088

__sync_fetch_and_nand as ANDC, even though that's
not what nand means.

llvm-svn: 56087

llvm-svn: 56085

multiplication overflows.

llvm-svn: 56082

condition. This fixes PR2740.

llvm-svn: 56076

llvm-svn: 56070

llvm-svn: 56069

llvm-svn: 56068

Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it.  This
was exposed by fast isel's handling of shifts on X86-64.  With this, FreeBench/pcompress2 passes on X86-64 in fast isel.

llvm-svn: 56067

to static allocas. As part of this change, refactor the
address mode code for laods and stores.

llvm-svn: 56066