Commits · 9e8a0393183878dcc3e31d8c7905bfd916e7a7fb · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Mar 19, 2015
- Add support for __nvvm_reflect changes in libdevice in CUDA-7.0 · 9e8a0393
  Artem Belevich authored Mar 19, 2015
  9e8a0393
- [Hexagon] Add support for vector instructions · 42113347
  Krzysztof Parzyszek authored Mar 19, 2015
  42113347
- [InstCombine] Don't fold a GEP into itself through a PHI node · 5add63f2
  Daniel Jasper authored Mar 19, 2015
  5add63f2
- Note that we don't support COFF on PPC. · 7f45440b
  Rafael Espindola authored Mar 19, 2015
  7f45440b
- llvm-cov: Only emit colour by default if the output is a tty · cfb53e49
  Justin Bogner authored Mar 19, 2015
  cfb53e49
Mar 18, 2015
- Fixed failing test due to missing target triple causing different results on different buildbots. · cf1d7df2
  Simon Pilgrim authored Mar 18, 2015
  cf1d7df2
- Teach getDefaultFormat that we only support ELF on some architectures. · 24254890
  Rafael Espindola authored Mar 18, 2015
  24254890
- [X86][SSE] Avoid scalarization of v2i64 vector shifts (REAPPLIED) · 5ec5c9ca
  Simon Pilgrim authored Mar 18, 2015
  5ec5c9ca
- Revert "[X86][SSE] Avoid scalarization of v2i64 vector shifts" as it · 050f590a
  Eric Christopher authored Mar 18, 2015
  050f590a
- Use WinEHPrepare to outline SEH finally blocks · 0f9e27a3
  Reid Kleckner authored Mar 18, 2015
  0f9e27a3
- [X86][SSE] Avoid scalarization of v2i64 vector shifts · 5c837edc
  Simon Pilgrim authored Mar 18, 2015
  5c837edc
- TableGen: Fix register class lane masks being too conservative. · 3b365331
  Matthias Braun authored Mar 18, 2015
  3b365331
- Handle X86::reloc_riprel_4byte in 32 bits mode. · 38438bae
  Rafael Espindola authored Mar 18, 2015
  38438bae
- Use utils/update_llc_test_checks.py to update all CHECKs · e4cdb8fc
  Sanjay Patel authored Mar 18, 2015
  e4cdb8fc
- [Hexagon] Intrinsics for circular and bit-reversed loads and stores · 47ab1f20
  Krzysztof Parzyszek authored Mar 18, 2015
  47ab1f20
- fixed to test features, not CPU model · e90d0387
  Sanjay Patel authored Mar 18, 2015
  e90d0387
- [Hexagon] Handle ENDLOOP0 in InsertBranch and RemoveBranch · 78cc36fe
  Krzysztof Parzyszek authored Mar 18, 2015
  78cc36fe
- Add support for .ifnes psuedo-op. · 51c3560c
  Sid Manning authored Mar 18, 2015
  51c3560c
- Change test to accept an additional critical edge split. · 9ec83403
  Daniel Jasper authored Mar 18, 2015
  9ec83403
- [ARM] Align stack objects passed to memory intrinsics · 0dbcd654
  John Brawn authored Mar 18, 2015
  0dbcd654
- Add missing newline to end of test file. · 2063cb63
  John Brawn authored Mar 18, 2015
  2063cb63
- Add testcases for BEXTR. · 89f5dec0
  Josh Magee authored Mar 18, 2015
  89f5dec0
- Missed testcase for r232577 · d5972bda
  Krzysztof Parzyszek authored Mar 18, 2015
  d5972bda
- [SCEV] Make isImpliedCond smarter. · cb8bca17
  Sanjoy Das authored Mar 18, 2015
  cb8bca17
- DAGCombiner: fold (xor (shl 1, x), -1) -> (rotl ~1, x) · e48237df
  David Majnemer authored Mar 18, 2015
  e48237df
- COFF: Let globals with private linkage reside in their own section · 7db449a6
  David Majnemer authored Mar 17, 2015
  7db449a6
- Fix bug while building FP16 constant vectors for AArch64 · 12aeefc6
  Pirama Arumuga Nainar authored Mar 17, 2015
  12aeefc6
Mar 17, 2015
- Add the option -no-symbolic-operands to llvm-objdump used with -macho and · 8e29ec9e
  Kevin Enderby authored Mar 17, 2015
  8e29ec9e
- Emit the offset directly instead of creating a dummy expression. · 7fce7e62
  Rafael Espindola authored Mar 17, 2015
  7fce7e62
- Add the option, -no-leading-addr llvm-objdump used with -macho and · ab5e6c99
  Kevin Enderby authored Mar 17, 2015
  ab5e6c99
- Revert "COFF: Let globals with private linkage reside in their own section" · 63b1d999
  David Majnemer authored Mar 17, 2015
  63b1d999
- COFF: Let globals with private linkage reside in their own section · 47e38429
  David Majnemer authored Mar 17, 2015
  47e38429
- Centralize the handling of unique ids for temporary labels. · 9ab09237
  Rafael Espindola authored Mar 17, 2015
  9ab09237
- TLI: Add addVectorizableFunctionsFromVecLib. · 6d8a2aa9
  Michael Zolotukhin authored Mar 17, 2015
  6d8a2aa9
- TTI: Honour cost model for estimating cost of vector-intrinsic and calls. · c3d60efb
  Michael Zolotukhin authored Mar 17, 2015
  c3d60efb
- [ARM] Fix offset calculation in ARMBaseRegisterInfo::needsFrameBaseReg · 30934c09
  Richard Barton authored Mar 17, 2015
  30934c09
- [SwitchLowering] Remove incoming values in the reverse order · 24fcae8f
  Michael Liao authored Mar 17, 2015
  24fcae8f
- Add the option, -dis-symname to llvm-objdump used with -macho and · 6a22175d
  Kevin Enderby authored Mar 17, 2015
  6a22175d
- asan: optimization experiments · 618d580e
  Dmitry Vyukov authored Mar 17, 2015
  618d580e
- Fix R0 use in PowerPC VSX store for FastIsel. · f6815601
  Samuel Antao authored Mar 17, 2015
  f6815601