but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.

llvm-svn: 27849

llvm-svn: 27847

  instructions.
- Fixed a commute vector_shuff bug.

llvm-svn: 27845

llvm-svn: 27840

llvm-svn: 27782

llvm-svn: 27779

llvm-svn: 27768

llvm-svn: 27767

llvm-svn: 27755

llvm-svn: 27719

llvm-svn: 27718

llvm-svn: 27711

llvm-svn: 27644

Clean up and fix various logical ops issues.

llvm-svn: 27633

llvm-svn: 27612

llvm-svn: 27575

llvm-svn: 27556

llvm-svn: 27501

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27444

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27434

llvm-svn: 27433

llvm-svn: 27427

Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

from a 128-bit vector.

llvm-svn: 27304

llvm-svn: 27275

llvm-svn: 27272

llvm-svn: 27271

Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

vector_shuffle undef.

llvm-svn: 27250

- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246

- Other shuffle related fixes.

llvm-svn: 27244

llvm-svn: 27239

llvm-svn: 27223

llvm-svn: 27222

* Bug fixes.

llvm-svn: 27218