It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.

Then the pseudo-instructions can go away.

llvm-svn: 162061

Use the target independent select analysis hooks.

llvm-svn: 162060

Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.

Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.

llvm-svn: 162059

llvm-svn: 162039

llvm-svn: 162037

llvm-svn: 162035

llvm-svn: 162034

llvm-svn: 162032

where some fact lake a=b dominates a use in a phi, but doesn't dominate the
basic block itself.

This feature could also be implemented by splitting critical edges, but at least
with the current algorithm reasoning about the dominance directly is faster.

The time for running "opt -O2" in the testcase in pr10584 is 1.003 times slower
and on gcc as a single file it is 1.0007 times faster.

llvm-svn: 162023

llvm-svn: 162014

Without fastcc support, the caller just falls through to CallingConv::C
for fastcc, but callee still uses fastcc, this inconsistency of calling
convention is a problem, and fastcc support can fix it.

llvm-svn: 162013

llvm-svn: 162012

llvm-svn: 162010

llvm-svn: 162009

floats.

llvm-svn: 162008

llvm-svn: 161995

The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.

This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.

llvm-svn: 161994

llvm-svn: 161990

llvm-svn: 161989

around. That's not how we do things. Besides, the commit message tells us that
it is covered by the GCC test suite.

------------------------------------------------------------------------
r127497 | zwarich | 2011-03-11 13:51:56 -0800 (Fri, 11 Mar 2011) | 3 lines

Fix the GCC test suite issue exposed by r127477, which was caused by stack
protector insertion not working correctly with unreachable code. Since that
revision was rolled out, this test doesn't actual fail before this fix.
------------------------------------------------------------------------

llvm-svn: 161985

allocations of executable memory would not be padded
to account for the size of the allocation header.
This resulted in undersized allocations, meaning that
when the allocation was written to later the next
allocation's header would be corrupted.

llvm-svn: 161984

This can be used to tell TableGen to use a specific SubRegIndex instead
of synthesizing one when discovering all sub-registers.

llvm-svn: 161982

llvm-svn: 161979

llvm-svn: 161978

llvm-svn: 161976

This should replace uses of:

class A {
  A(const &A); // DO NOT IMPLEMENT
public:
  ...
};

llvm-svn: 161975

Patch by Andy Gibbs <andyg1001@hotmail.co.uk>

llvm-svn: 161973

Fix another roundToIntegral bug where very large values could become infinity.  Problem and solution identified by Steve Canon.

llvm-svn: 161969

TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.

Also take this opportunity to stop creating new Record objects for
synthetic indexes.

llvm-svn: 161964

Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029

llvm-svn: 161962

llvm-svn: 161956

When predicating this instruction:

  Rd = ADD Rn, Rm

We need an extra operand to represent the value given to Rd when the
predicate is false:

  Rd = ADDCC Rfalse, Rn, Rm, pred

The Rd and Rfalse operands are different registers while in SSA form.
Rfalse is tied to Rd to make sure they get the same register during
register allocation.

Previously, Rd and Rn were tied, but that is not required.

Compare to MOVCC:

  Rd = MOVCC Rfalse, Rtrue, pred

llvm-svn: 161955

instruction to something absurdly high, while setting the probability of
branching to the 'unwind' destination to the bare minimum. This should set cause
the normal destination's invoke blocks to be moved closer to the invoke.

PR13612

llvm-svn: 161944

llvm-svn: 161940

[asan] implement --asan-always-slow-path, which is a part of the improvement to handle unaligned partially OOB accesses. See http://code.google.com/p/address-sanitizer/issues/detail?id=100

llvm-svn: 161937

Fix a problem with APFloat::roundToIntegral where it would return incorrect results for negative inputs to trunc.  Add unit tests to verify this behavior.

llvm-svn: 161929

- memcpy size is wrongly truncated into 32-bit and treat 8GB memcpy is
  0-sized memcpy
- as 0-sized memcpy/memset is already removed before SimplifyMemTransfer
  and SimplifyMemSet in visitCallInst, replace 0 checking with
  assertions.
- replace getZExtValue() with getLimitedValue() according to
  Eli Friedman

llvm-svn: 161923

Patch by Stephen Hines!

llvm-svn: 161921

pointer.

llvm-svn: 161919

reversed. This leads to wrong codegen for float-to-half conversion
intrinsics which are used to support storage-only fp16 type.
NEON variants of same instructions are fine.

llvm-svn: 161907