Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.

llvm-svn: 74731

Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.

llvm-svn: 74580

llvm-svn: 74549

llvm-svn: 74543

llvm-svn: 74385

llvm-svn: 74384

Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329

This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919

(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).

llvm-svn: 73529

llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).

llvm-svn: 71758

booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722

a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.

llvm-svn: 71610

When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545

llvm-svn: 68405

llvm-svn: 68404

llvm-svn: 64891

llvm-svn: 64429

Modify callers.

llvm-svn: 64409

llvm-svn: 64342

suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.

llvm-svn: 64124

llvm-svn: 63938

created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.

llvm-svn: 63584

llvm-svn: 62600

llvm-svn: 60851

parts, and add target-independent code to add/preserve
MachineMemOperands.

llvm-svn: 60488

llvm-svn: 59542

llvm-svn: 58643

llvm-svn: 57622

isReg, etc., from isRegister, etc.

llvm-svn: 57006

was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375

Convert uses of std::vector in TargetInstrInfo to SmallVector.  This change had to be propoagated down into all the targets and up into all clients of this API.

llvm-svn: 54802

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.

llvm-svn: 53097

Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented

llvm-svn: 49809

llvm-svn: 48995

patch by David Chisnall.

llvm-svn: 48963

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380