llvm-svn: 116742

llvm-svn: 116741

llvm-svn: 116738

Read/write declaration attributes from/to PCH properly. Embed them in the declaration block instead of trying to create another block.

The new block was messing with the assumption that after decls block comes the stmts block.
Fixes http://llvm.org/PR8406

llvm-svn: 116737

llvm-svn: 116736

executing properly.

llvm-svn: 116735

Patch by Alexander Herz!

llvm-svn: 116733

is currently inert by default.

llvm-svn: 116732

llvm-svn: 116731

llvm-svn: 116730

base register is available. rdar://8525298

llvm-svn: 116729

llvm-svn: 116728

the termios settings on the debugger's input handle.

llvm-svn: 116725

(after - or +), always traverse superclasses and all categories. The
programmer may want to complete a method from *anywhere*.

llvm-svn: 116723

option to enable it.

llvm-svn: 116722

llvm-svn: 116721

does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.

Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.

Update tests to explicitly request -basicaa.

llvm-svn: 116720

llvm-svn: 116719

Also add a more useful assert message for test_set_output_path(), which is currently decorated
with @expectedFailure.

llvm-svn: 116718

synthesized property. // rdar: //8498026

llvm-svn: 116717

be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716

start for consistency.

llvm-svn: 116715

offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

llvm-svn: 116714

Update atomic Design A spec with reference C++ implementations for the purpose of documeting the semantics of each atomic operation.

llvm-svn: 116713

llvm-svn: 116712

llvm-svn: 116711

llvm-svn: 116710

llvm-svn: 116709

llvm-svn: 116707

Also change the utility functions in lldbutil.py, too, to correspond to the StateType representation change.

llvm-svn: 116706

llvm-svn: 116705

1. enum underlying type is int by default.
2. Error "enumerator value is not representable in the underlying type"is a ExtWarning

llvm-svn: 116704

llvm-svn: 116703

-ast-print-xml, from Martin Vejnar!

llvm-svn: 116702

The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.

llvm-svn: 116701

llvm-svn: 116700

llvm-svn: 116699

working just fine.

llvm-svn: 116698

but something is still killing our inferior.

Fixed an issue with darwin-debug where it wasn't passing all needed arguments
to the inferior.

Fixed a race condition with the attach to named process code.

llvm-svn: 116697

llvm-svn: 116696