llvm-svn: 139622

Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.

llvm-svn: 139610

llvm-svn: 139607

llvm-svn: 139606

Only disassembler instructions with vvvv != 1111 if the instruction actually uses the vvvv field to encode an operand. Fixes PR10851.

llvm-svn: 139591

Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.

llvm-svn: 139588

Fix encoding of VMOVDQU to not simultaneously be 'TB OpSize' and 'XS'. 'XS' is correct and seems to have been taking priority.

llvm-svn: 139587

llvm-svn: 139575

Fix the assembler strings for a couple of atomic instructions.  Doesn't really matter much in practice, but it's a bit cleaner.

llvm-svn: 139563

llvm-svn: 139559

destination types are equal!

llvm-svn: 139553

llvm-svn: 139542

llvm-svn: 139541

llvm-svn: 139537

There's no need to add additional predicate operands when converting a tB to a tBfar now.  Fixes nightly test failures on armv6 Thumb.  <rdar://problem/10110404>

llvm-svn: 139531

However with this fix it does now.

Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.

llvm-svn: 139528

llvm-svn: 139527

llvm-svn: 139526

llvm-svn: 139525

Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.

llvm-svn: 139522

This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495

llvm-svn: 139494

llvm-svn: 139491

Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.

llvm-svn: 139486

llvm-svn: 139485

Undo the changes from r139285 which added custom lowering to vselect.
Add tablegen lowering for vselect.

llvm-svn: 139479

r139454 activates an assert in a case where we were doing the right thing anyway.  Make that explicit, and un-XFAIL the testcase.

llvm-svn: 139458

lib/ExecutionEngine/MCJIT/MCJIT.cpp from:

  assert("error");

to:

  assert(0 && "error");

llvm-svn: 139456

  assert("not implemented for target shuffle node");

to:

  assert(0 && "not implemented for target shuffle node");

This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.

llvm-svn: 139454

Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440

llvm-svn: 139432

llvm-svn: 139431

llvm-svn: 139429

llvm-svn: 139422

llvm-svn: 139421

llvm-svn: 139420

Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.

llvm-svn: 139415

llvm-svn: 139412

llvm-svn: 139405

Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type

llvm-svn: 139400