llvm-svn: 68610

llvm-svn: 68607

llvm-svn: 68603

Emit .line debug directives for stoppoints. The debug location is retrieved by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes.

llvm-svn: 68602

integer types, unless they are already strange.  This prevents it from
turning the code produced by SROA into crazy libcalls and stuff that 
the code generator can't handle.  In the attached example, the result
was an i96 multiply that caused the x86 backend to assert.

Note that if TargetData had an idea of what the legal types are for
a target that this could be used to stop instcombine from introducing
i64 muls, as Scott wanted.

llvm-svn: 68598

Every function has the address of its frame in the beginning of code section.
The frame address is retrieved and used to pass arguments.

llvm-svn: 68597

a testcase I'm about to attach to that pr.

llvm-svn: 68592

abstraction for CommandLine.

llvm-svn: 68588

llvm-svn: 68580

using an lea in place of a mov and an add for this test.

llvm-svn: 68579

avoiding sign extension for the top octet.  For "negative" chars, we'd print
stuff like:

.asciz	"\702...
now we print:
.asciz	"\302...

llvm-svn: 68577

with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce
SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG
instructions), and teach the DAGCombiner to take advantage of this on
targets which support it. This eliminates many redundant
zero-extension operations on x86-64.

This adds a new TargetLowering hook, isZExtFree. It's similar to
isTruncateFree, except it only applies to actual definitions, and not
no-op truncates which may not zero the high bits.

Also, this adds a new optimization to SimplifyDemandedBits: transform
operations like x+y into (zext (add (trunc x), (trunc y))) on targets
where all the casts are no-ops. In contexts where the high part of the
add is explicitly masked off, this allows the mask operation to be
eliminated. Fix the DAGCombiner to avoid undoing these transformations
to eliminate casts on targets where the casts are no-ops.

Also, this adds a new two-address lowering heuristic. Since
two-address lowering runs before coalescing, it helps to be able to
look through copies when deciding whether commuting and/or
three-address conversion are profitable.

Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle
the case that a clobber range extended both before and beyond an
existing live range. In that case, multiple live ranges need to be
added. This was exposed by the new subreg coalescing code.

Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the
spiller behavior it was looking for no longer occurrs with the new
instruction selection.

llvm-svn: 68576

llvm-svn: 68569

builds.

--- Reverse-merging (from foreign repository) r68552 into '.':
U    test/CodeGen/X86/tls8.ll
U    test/CodeGen/X86/tls10.ll
U    test/CodeGen/X86/tls2.ll
U    test/CodeGen/X86/tls6.ll
U    lib/Target/X86/X86Instr64bit.td
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86RegisterInfo.cpp
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86CodeEmitter.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86InstrInfo.h
U    lib/Target/X86/X86ISelDAGToDAG.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U    lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U    lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U    lib/Target/X86/X86ISelLowering.h
U    lib/Target/X86/X86InstrInfo.cpp
U    lib/Target/X86/X86InstrBuilder.h
U    lib/Target/X86/X86RegisterInfo.td

llvm-svn: 68560

Right now DBG_LABEL are required for llvm.dbg.region_start and llvm.dbg.region_end in non-fast mode also.

llvm-svn: 68559

This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.

Will work on it and on X86-64 support.

llvm-svn: 68552

SelectionDAG do those. This fixes PR3955.

llvm-svn: 68546

When compiling in Thumb mode, only the low (R0-R7) registers are available
for most instructions. Breaking the low registers into a new register class
handles this. Uses of R12, SP, etc, are handled explicitly where needed
with copies inserted to move results into low registers where the rest of
the code generator can deal with them.

llvm-svn: 68545

llvm-svn: 68544

llvm-svn: 68542

llvm-svn: 68534

llvm-svn: 68531

work.

llvm-svn: 68530

llvm-svn: 68528

Types can have references to eachother, so we can't just call destroy on them.

llvm-svn: 68523

Thanks to Duncan for noticing this

llvm-svn: 68518

llvm-svn: 68500

them by reference, instead of packing each byte into a
smallvector.

llvm-svn: 68486

llvm-svn: 68485

llvm-svn: 68472

llvm-svn: 68471

without converting each byte to a uint64_t to stick in a SmallVector.

llvm-svn: 68469

elements in a form that is efficient for the reader to just get a
pointer in memory and start reading.  APIs to do efficient reading
and writing are still todo.

llvm-svn: 68465

Patch by Richard Pennington.

llvm-svn: 68464

llvm-svn: 68463

llvm-svn: 68462

llvm-svn: 68461

llvm-svn: 68460

llvm-svn: 68459

llvm-svn: 68458