llvm-svn: 160948

Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.

llvm-svn: 160946

llvm-svn: 160945

llvm-svn: 160852

These tables were indexed by [register][subreg index] which made them,
very large and sparse.

Replace them with lists of sub-register indexes that match the existing
lists of sub-registers. MCRI::getSubReg() becomes a very short linear
search, like getSubRegIndex() already was.

llvm-svn: 160843

Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone,
there is no longer a need for the CompositeIndices construct in .td
files. Sub-register index composition can be specified on the
SubRegIndex itself using the ComposedOf field.

Also enforce unique names for sub-registers in TableGen. The same
sub-register cannot be available with multiple sub-register indexes.

llvm-svn: 160842

llvm-svn: 160775

This simplifies MCRegisterInfo and shrinks the target descriptions a bit
more.

llvm-svn: 160758

llvm-svn: 160621

is one more that MRM_DF which is 55.  Previously, it held value 45, the same
as MRM_D0.

llvm-svn: 160465

llvm-svn: 160463

Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.

llvm-svn: 160420

A standalone pattern defined in a multiclass expansion should handle
null_frag references just like patterns on instructions. Follow-up to
r160333.

llvm-svn: 160384

Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.

For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
  def _x : myI<(outs rc:), (ins rc:), []>;
  def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}

defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;

llvm-svn: 160333

Defer checking for registers in the MC AsmMatcher until the after user-defined match classes have been checked.  This allows the creation of MatchClass's that are supersets of a register class.

llvm-svn: 160327

Make sure the tblgen'erated asm matcher correctly returns numoperands+1
as the ErrorInfo when the problem was that there weren't enough operands
specified.

rdar://9142751

llvm-svn: 160144

llvm-svn: 160110

llvm-svn: 159959

subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891

llvm-svn: 159890

llvm-svn: 159889

llvm-svn: 159543

Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.

llvm-svn: 159541

This reverts commit r159406. I noticed a performance regression so I'll back out for now.

llvm-svn: 159411

The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.

Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.

llvm-svn: 159406

llvm-svn: 159334

llvm-svn: 159316

Patch by Ivan Llopard!

llvm-svn: 159281

Don't override a custom diagnostic w/ a generic InvalidOperand, all else
being equal.

llvm-svn: 159238

Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256

Modified Disassembler to handle VSIB addressing mode.

llvm-svn: 159221

When generating selection tables for Pat instances, TableGen relied on
an output Instruction's Pattern field being set to infer whether a
chain should be added.

This patch adds additional logic to check various flag fields so that
correct code can be generated even if Pattern is unset.

llvm-svn: 159217

"Invalid operand" may be a completely correct diagnostic, but it's often
insufficiently specific to really help identify and fix the problem in
assembly source. Allow a target to specify a more-specific diagnostic kind
for each AsmOperandClass derived definition and use that to provide
more detailed diagnostics when an operant of that class resulted in a
match failure.

rdar://8987109

llvm-svn: 159050

Original commit message:
    Allow up to 64 functional units per processor itinerary.

    This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
    This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 159027

This makes it explicit when ScoreboardHazardRecognizer will be used.
"GenericItineraries" would only make sense if it contained real
itinerary values and still required ScoreboardHazardRecognizer.

llvm-svn: 158963

This patch changes the type used to hold the FU bitset from unsigned to uint64_t.
This will be needed for some upcoming PowerPC itineraries.

llvm-svn: 158679

When returning a 'cannot match due to missing CPU features' error code,
if there are multiple potential matches with different feature sets,
return the smallest set of missing features from the alternatives as
that's most likely to be the one that's desired.

llvm-svn: 158673

There is otherwise not a newline between the CPU name and the start of the next
pass's output which makes both difficult to read.

llvm-svn: 158350

The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

llvm-svn: 158311

This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

llvm-svn: 158215

Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a complex operand are called out explicitly in the asm string.

llvm-svn: 158183