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  1. Mar 26, 2014
    • Timur Iskhodzhanov's avatar
    • Daniel Sanders's avatar
      [mips] $s8 is an alias for $fp in all ABI's, not just N32/N64. · 85f482b0
      Daniel Sanders authored
      llvm-svn: 204793
      85f482b0
    • Daniel Sanders's avatar
      [mips] Move the CHECK lines in mips*-register-names.s to make it more obvious... · 91d4407c
      Daniel Sanders authored
      [mips] Move the CHECK lines in mips*-register-names.s to make it more obvious which CHECK matches with which insn
      
      This reveals a small mistake in mips-register-names.s ($sp is tested twice and
      $s8 is not tested) which will be fixed in a follow-up commit.
      
      llvm-svn: 204792
      91d4407c
    • Timur Iskhodzhanov's avatar
      Add tests for r204790 · 6a35c155
      Timur Iskhodzhanov authored
      llvm-svn: 204791
      6a35c155
    • Timur Iskhodzhanov's avatar
      Fix PR19239 - Add support for generating debug info for functions without... · 8499a122
      Timur Iskhodzhanov authored
      Fix PR19239 - Add support for generating debug info for functions without lexical scopes and/or debug info at all
      
      llvm-svn: 204790
      8499a122
    • Timur Iskhodzhanov's avatar
      Use -LABEL checks in the COFF debug info tests · e32ef937
      Timur Iskhodzhanov authored
      llvm-svn: 204788
      e32ef937
    • Rafael Espindola's avatar
      Revert "Prevent alias from pointing to weak aliases." · 65481d7b
      Rafael Espindola authored
      This reverts commit r204781.
      
      I will follow up to with msan folks to see what is what they
      were trying to do with aliases to weak aliases.
      
      llvm-svn: 204784
      65481d7b
    • Hal Finkel's avatar
      [PowerPC] Generate logical vector VSX instructions · bd4de9d4
      Hal Finkel authored
      These instructions are essentially the same as their Altivec counterparts, but
      have access to the larger VSX register file.
      
      llvm-svn: 204782
      bd4de9d4
    • Rafael Espindola's avatar
      Prevent alias from pointing to weak aliases. · 3b712a84
      Rafael Espindola authored
      Aliases are just another name for a position in a file. As such, the
      regular symbol resolutions are not applied. For example, given
      
      define void @my_func() {
        ret void
      }
      @my_alias = alias weak void ()* @my_func
      @my_alias2 = alias void ()* @my_alias
      
      We produce without this patch:
      
              .weak   my_alias
      my_alias = my_func
              .globl  my_alias2
      my_alias2 = my_alias
      
      That is, in the resulting ELF file my_alias, my_func and my_alias are
      just 3 names pointing to offset 0 of .text. That is *not* the
      semantics of IR linking. For example, linking in a
      
      @my_alias = alias void ()* @other_func
      
      would require the strong my_alias to override the weak one and
      my_alias2 would end up pointing to other_func.
      
      There is no way to represent that with aliases being just another
      name, so the best solution seems to be to just disallow it, converting
      a miscompile into an error.
      
      llvm-svn: 204781
      3b712a84
    • David Blaikie's avatar
      DebugInfo: Add fission-related sections to COFF · 62dd7df6
      David Blaikie authored
      Allows this test to pass on COFF platforms so we don't need to restrict
      this test to a single target anymore.
      
      llvm-svn: 204780
      62dd7df6
    • Rafael Espindola's avatar
      Correctly detect if a symbol uses a reserved section index or not. · 85a8491a
      Rafael Espindola authored
      The logic was incorrect for variables, causing them to end up in the wrong
      section if the section had an index >= 0xff00.
      
      llvm-svn: 204771
      85a8491a
    • Quentin Colombet's avatar
      [X86] Add broadcast instructions to the table used by ExeDepsFix pass. · 6f12ae0d
      Quentin Colombet authored
      Adds the different broadcast instructions to the ReplaceableInstrsAVX2 table.
      That way the ExeDepsFix pass can take better decisions when AVX2 broadcasts are
      across domain (int <-> float).
      
      In particular, prior to this patch we were generating:
        vpbroadcastd  LCPI1_0(%rip), %ymm2
        vpand %ymm2, %ymm0, %ymm0
        vmaxps  %ymm1, %ymm0, %ymm0 ## <- domain change penalty
      
      Now, we generate the following nice sequence where everything is in the float
      domain:
        vbroadcastss  LCPI1_0(%rip), %ymm2
        vandps  %ymm2, %ymm0, %ymm0
        vmaxps  %ymm1, %ymm0, %ymm0
      
      <rdar://problem/16354675>
      
      llvm-svn: 204770
      6f12ae0d
    • Rafael Espindola's avatar
      Create .symtab_shndxr only when needed. · 10be0837
      Rafael Espindola authored
      We need .symtab_shndxr if and only if a symbol references a section with an
      index >= 0xff00.
      
      The old code was trying to figure out if the section was needed ahead of time,
      making it a fairly dependent on the code actually writing the table. It was
      also somewhat conservative and would create the section in cases where it was
      not needed.
      
      If I remember correctly, the old structure was there so that the sections were
      created in the same order gas creates them. That was valuable when MC's support
      for ELF was new and we tested with elf-dump.py.
      
      This patch refactors the symbol table creation to another class and makes it
      obvious that .symtab_shndxr is really only created when we are about to output
      a reference to a section index >= 0xff00.
      
      While here, also improve the tests to use macros. One file is one section
      short of needing .symtab_shndxr, the second one has just the right number.
      
      llvm-svn: 204769
      10be0837
    • Hal Finkel's avatar
      [PowerPC] Select between VSX A-type and M-type FMA instructions just before RA · 174e5909
      Hal Finkel authored
      The VSX instruction set has two types of FMA instructions: A-type (where the
      addend is taken from the output register) and M-type (where one of the product
      operands is taken from the output register). This adds a small pass that runs
      just after MI scheduling (and, thus, just before register allocation) that
      mutates A-type instructions (that are created during isel) into M-type
      instructions when:
      
       1. This will eliminate an otherwise-necessary copy of the addend
      
       2. One of the product operands is killed by the instruction
      
      The "right" moment to make this decision is in between scheduling and register
      allocation, because only there do we know whether or not one of the product
      operands is killed by any particular instruction. Unfortunately, this also
      makes the implementation somewhat complicated, because the MIs are not in SSA
      form and we need to preserve the LiveIntervals analysis.
      
      As a simple example, if we have:
      
      %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
      %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
                              %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
        ...
        %vreg9<def,tied1> = XSMADDADP %vreg9<tied0>, %vreg17, %vreg19,
                              %RM<imp-use>; VSLRC:%vreg9,%vreg17,%vreg19
        ...
      
      We can eliminate the copy by changing from the A-type to the
      M-type instruction. This means:
      
        %vreg5<def,tied1> = XSMADDADP %vreg5<tied0>, %vreg17, %vreg16,
                              %RM<imp-use>; VSLRC:%vreg5,%vreg17,%vreg16
      
      is replaced by:
      
        %vreg16<def,tied1> = XSMADDMDP %vreg16<tied0>, %vreg18, %vreg9,
                              %RM<imp-use>; VSLRC:%vreg16,%vreg18,%vreg9
      
      and we remove: %vreg5<def> = COPY %vreg9; VSLRC:%vreg5,%vreg9
      
      llvm-svn: 204768
      174e5909
    • NAKAMURA Takumi's avatar
  2. Mar 25, 2014
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