register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529

llvm-svn: 127642

Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127498

created from the", it broke some GCC test suite tests.

llvm-svn: 127477

lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.

This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.

llvm-svn: 127459

The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

llvm-svn: 127354

* Add tests for VSRI and VSLI.

llvm-svn: 127297

llvm-svn: 127294

* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293

llvm-svn: 127209

expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193

that contain only letters, digits and the characters "_" and ".".

llvm-svn: 127028

llvm-svn: 126987

llvm-svn: 126970

llvm-svn: 126963

for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.

llvm-svn: 126933

llvm-svn: 126931

Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915

Patch by Ted Kremenek!

llvm-svn: 126895

shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723

needed two predicate operands before the imm operand.

llvm-svn: 126662

test isn't run when the arm backend isn't built.  This
fixes PR9327

llvm-svn: 126500

Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.

llvm-svn: 126443

llvm-svn: 126401

llvm-svn: 126337

enabled for all targets. Non-X86 targets should not have this behavior
enabled by default.

Joerg, if you would like to resubmit with the behavior conditionalized to be
X86-ELF only, that's fine.

llvm-svn: 126336

Fixes PR9292.

llvm-svn: 126330

it to ignore valid uses of FS and GS as additional
base registers in address computations.  Added a test
case for this.

llvm-svn: 126302

llvm-svn: 126244

fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.

llvm-svn: 126182

From Dimitry Andric.

llvm-svn: 126168

Patch by Jai Menon.

llvm-svn: 126165

llvm-svn: 126157

PR9245.

llvm-svn: 126091

This is reasonable to do since all bt-mem forms do the
same thing.

llvm-svn: 126047

testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948

llvm-svn: 125805

Validate encoding of leave in 64bit mode.

llvm-svn: 125795

the right thing and stop trying to copy it. Fixes PR8944.

llvm-svn: 125648

llvm-svn: 125629

This is submitted by Joerg Sonnenberger and fixes his PR8685.

llvm-svn: 125595