Commits · b7a5469c7eb9980ba22b6f43459b8fb42a7ba6e3 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Feb 16, 2018
- [WebAssembly] MC: Make explicit our current lack of support for relocations... · b7a5469c
  Sam Clegg authored Feb 16, 2018
  b7a5469c
- AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction. · da38b5fd
  Changpeng Fang authored Feb 16, 2018
  da38b5fd
- [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles... · 4e2f757d
  Simon Pilgrim authored Feb 16, 2018
  4e2f757d
- [PowerPC] Fix transform in table gen file causing UB · 6cf41b02
  Nemanja Ivanovic authored Feb 16, 2018
  6cf41b02
- [mips] Remove codegen support from some 16 bit instructions · b8ae30ec
  Simon Dardis authored Feb 16, 2018
  b8ae30ec
- [ARM] Return true in enableMultipleCopyHints(). · 995ba6e4
  Jonas Paulsson authored Feb 16, 2018
  995ba6e4
- [ARM] Materialise some boolean values to avoid a branch · d41059a9
  Roger Ferrer Ibanez authored Feb 16, 2018
  d41059a9
- [X86] Allow CMOVs of constants to be sign extended from i32. · 2e4b838c
  Craig Topper authored Feb 16, 2018
  2e4b838c
- [X86] Don't zero_extend cmov up to i64, stop at i32. · 5d9e3010
  Craig Topper authored Feb 16, 2018
  5d9e3010
Feb 15, 2018
- [AMDGPU] Combine adjacent waitcounts in a single strongest wait · ff2763a6
  Stanislav Mekhanoshin authored Feb 15, 2018
  ff2763a6
- [X86][3DNOW] Teach decoder about AMD 3DNow! instrs · de9ad4ba
  Rafael Auler authored Feb 15, 2018
  de9ad4ba
- [X86] Enable BT to be used in place of TEST for single bit checks under optsize · f3f35efe
  Craig Topper authored Feb 15, 2018
  f3f35efe
- [X86] Use btc/btr/bts to implement xor/and/or that affects a single bit in the... · 2b2d8c5e
  Craig Topper authored Feb 15, 2018
  2b2d8c5e
- Recommit [Hexagon] Make the vararg handling a bit more robust · e0d7de7d
  Krzysztof Parzyszek authored Feb 15, 2018
  e0d7de7d
- bpf: fix a bug in dag2dag optimization for loads from readonly section · 920df52a
  Yonghong Song authored Feb 15, 2018
  920df52a
- Revert "[Hexagon] Make the vararg handling a bit more robust" · 8a9eff6b
  Krzysztof Parzyszek authored Feb 15, 2018
  8a9eff6b
- [Hexagon] Make the vararg handling a bit more robust · 56810727
  Krzysztof Parzyszek authored Feb 15, 2018
  56810727
- [Hexagon] Fix lowering of formal arguments after r324737 · 18e0d2a1
  Krzysztof Parzyszek authored Feb 15, 2018
  18e0d2a1
- [ARM] Allow 64- and 128-bit types with 't' inline asm constraint · e28cb839
  Pablo Barrio authored Feb 15, 2018
  e28cb839
- [X86][SSE] combineTruncateWithSat - use truncateVectorWithPACK to chain PACKUS... · 17bb6f07
  Simon Pilgrim authored Feb 15, 2018
  17bb6f07
- [X86][SSE] combineTruncateWithSat - use truncateVectorWithPACK to chain PACKSS... · 908f833e
  Simon Pilgrim authored Feb 15, 2018
  908f833e
- [ARM] f16 vcmp fixes · 9430c8cd
  Sjoerd Meijer authored Feb 15, 2018
  9430c8cd
- [X86] Change 32 and 64 bit versions of LSL instruction have a 16-bit memory operand. · 386cfa08
  Craig Topper authored Feb 15, 2018
  386cfa08
- [X86] Dont' allow 'outs' and 'ins' in at&t syntax without suffixes. · bab7b0a4
  Craig Topper authored Feb 14, 2018
  bab7b0a4
- [X86] Reverse the operand order of invlpga in at&t syntax to match gas. · a08f83ba
  Craig Topper authored Feb 14, 2018
  a08f83ba
Feb 14, 2018
- [X86] Don't swap argument on BOUND instruction in at&t syntax. · 67575216
  Craig Topper authored Feb 14, 2018
  67575216
- [Hexagon] Split HVX vector pair loads/stores, expand unaligned loads · ad83ce4c
  Krzysztof Parzyszek authored Feb 14, 2018
  ad83ce4c
- [X86][SSE] truncateVectorWithPACK - Use src type instead of dst to select between PACK*SDW/PACK*SWB · 2ec83736
  Simon Pilgrim authored Feb 14, 2018
  2ec83736
- [AMDGPU] Remove non-temporal flag from argument loads · c078ca92
  Stanislav Mekhanoshin authored Feb 14, 2018
  c078ca92
- [DWARF] Fix incorrect prologue end line record. · ee88ed67
  Paul Robinson authored Feb 14, 2018
  ee88ed67
- [ARM] f16 stack spill/reloads · 3b4294ed
  Sjoerd Meijer authored Feb 14, 2018
  3b4294ed
- Fix GCC -Wlogical-op-parentheses warning. NFCI. · ded6e7a2
  Simon Pilgrim authored Feb 14, 2018
  ded6e7a2
- [X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346 · fe1016c4
  Lama Saba authored Feb 14, 2018
  fe1016c4
- [X86][SSE] Relax type legality for combineTruncateWithSat PACKSS/PACKUS truncation · 86d15bff
  Simon Pilgrim authored Feb 14, 2018
  86d15bff
- [X86] Remove dead code from retpoline thunk generation · 1631ac16
  Reid Kleckner authored Feb 14, 2018
  1631ac16
- [globalisel][legalizerinfo] Follow up on post-commit review comments after r323681 · 7fc87360
  Daniel Sanders authored Feb 13, 2018
  7fc87360
Feb 13, 2018
- [X86] Use EDI for retpoline when no scratch regs are left · 91e11a83
  Reid Kleckner authored Feb 13, 2018
  91e11a83
- Revert r324903 "[AArch64] Refactor identification of SIMD immediates" · f381e94a
  Hans Wennborg authored Feb 13, 2018
  f381e94a
- [AMDGPU] Change constant addr space to 4 · 0124b548
  Yaxun Liu authored Feb 13, 2018
  0124b548
- [X86] Add combine to shrink 64-bit ands when one input is an any_extend and... · 036789a7
  Craig Topper authored Feb 13, 2018
  036789a7