Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.

llvm-svn: 138997

llvm-svn: 138948

Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810

Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

llvm-svn: 138771

Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.

llvm-svn: 138675

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552

Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488

Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.

llvm-svn: 138445

llvm-svn: 138351

Patch by Micah Villmow!

llvm-svn: 138330

llvm-svn: 138073

llvm-svn: 138067

Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid.  Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.

llvm-svn: 137830

llvm-svn: 137742

It turns out that the use of "__extension__" in these macros was disabling
the expected "incompatible pointer" warnings, so these type checks were not
doing anything anyway.  They introduced a serious bug by evaluating some
macro arguments twice, which is a big problem for arguments with side effects.
I'll have to find another way to get the right type checking.  Radar 9947657.

llvm-svn: 137680

Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675

No need for it to be redefined as part of every derived target asm parser
class.

llvm-svn: 137649

Use an Init (ultimately a StringInit) to represent the Record name.
This allows the name to be composed by standard TableGen operators.
This will enable us to get rid of the ugly #NAME# hack processing and
naturally replace it with operators.  It also increases flexibility
and power of the TableGen language by allowing record identifiers to
be computed dynamically.

llvm-svn: 137232

Add a method to return an Init as an unquoted string.  This primarily
affects StringInit where we return the value without surrounding it
with quotes.

This is in preparation for removing the ugly #NAME# hack and replacing
it with standard TabelGen operators.

llvm-svn: 137231

Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.

llvm-svn: 137171

Create a new register class for the set of all GPRs except the PC.  Use it to tighten our decoding of BFI.

llvm-svn: 137168

This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144

Fix encodings for Thumb ASR and LSR immediate operands.  They encode the range 1-32, with 32 encoded as 0.

llvm-svn: 137062

LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets.  Add an appropriate immediate type for them.

llvm-svn: 136896

Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845

Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704

Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.

llvm-svn: 136660

The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks.

llvm-svn: 136645

llvm-svn: 136635

llvm-svn: 136534

Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531

llvm-svn: 136511

Make sure DagInits are unique and created only once.

llvm-svn: 136501

Make sure FieldInits are unique and created only once.

llvm-svn: 136500

Make sure VarListElementInits are unique and created only once.

llvm-svn: 136499

Make sure VarBitInits are unique and created only once.

llvm-svn: 136498

Make sure VarInits are unique and created only once.

llvm-svn: 136497

Make sure TernOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

llvm-svn: 136496

Make sure BinOpInits are unique and created only once.  This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.

llvm-svn: 136495