register is available and when it's profitable.

e.g.
     xorq  %r12<kill>, %r13
     addq  %rax, -184(%rbp)
     addq  %r13, -184(%rbp)
==>
     xorq  %r12<kill>, %r13
     movq  -184(%rbp), %r12
     addq  %rax, %r12
     addq  %r13, %r12
     movq  %r12, -184(%rbp)

Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.

llvm-svn: 69341

the subreg field to 0, since the subreg field is only used
for virtual register subregs. This doesn't change
current functionality; it just eliminates bogus noise from
debug output.

llvm-svn: 68955

register destinations that are tied to source operands.  The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly.  The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).

llvm-svn: 68714

llvm-svn: 68099

llvm-svn: 68092

llvm-svn: 68059

llvm-svn: 67372

llvm-svn: 67335

Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded.

llvm-svn: 67068

llvm-svn: 67000

llvm-svn: 66780

Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files.  No (intended) functionality change.

llvm-svn: 66720

Yet another case where the spiller marked two uses of the same register on the same instruction as kill. This fixes PR3706.

llvm-svn: 66428

llvm-svn: 66363

llvm-svn: 65679

llvm-svn: 65498

If an available register falls through to a succ block, unset the last kill. Sorry, it's impossible to reduce a sensible test case. It basically requires the moon and stars to align in order to cause a failure.

llvm-svn: 65497

A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes.

llvm-svn: 64745

llvm-svn: 64428

the new way, where all of the information is passed on SDNodes and machine
instructions.

llvm-svn: 64427

llvm-svn: 64381

It's (currently) not safe to keep certain physical registers live across basic blocks, e.g. x86 fp stack registers.

llvm-svn: 64374

If availability info is kept when fallthrough into a bb, add the available registers to live-in set.

llvm-svn: 64372

Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction.

llvm-svn: 64339

Implement PR3495: local spiller optimization. The local spiller can now keep availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies.

llvm-svn: 64298

llvm-svn: 63599

llvm-svn: 62600

llvm-svn: 60392

Patch by Lang Hames!

llvm-svn: 57720

llvm-svn: 57673

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

ENABLE_EXPENSIVE_CHECKS for finding this.

llvm-svn: 57181

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 56085

llvm-svn: 56065

Fix an overly strict assertion. Source register of a copy may not be killed, it may be killed by an implicit super-register use.

llvm-svn: 55762

llvm-svn: 54968

llvm-svn: 54375

llvm-svn: 53766

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212