llvm-svn: 99428

NVCVTFrm will later be used to describe "vcvt with fractional bits".

llvm-svn: 99415

N3VX instructions using special case code.

llvm-svn: 99409

llvm-svn: 99402

llvm-svn: 99376

respectively, and add some more comment.

llvm-svn: 99373

test run permformance numbers say as to whether it helps.

llvm-svn: 99355

llvm-svn: 99344

llvm-svn: 99328

llvm-svn: 99327

Converted some of the NEON vcvt instructions to this format.

llvm-svn: 99326

llvm-svn: 99322

These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP.  The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.

llvm-svn: 99309

llvm-svn: 99295

Ref: A7.4.6 One register and a modified immediate value.

llvm-svn: 99288

llvm-svn: 99266

of D registers.  Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.

llvm-svn: 99265

of D registers.  Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.

llvm-svn: 99261

llvm-svn: 99201

llvm-svn: 99192

corresponding NEON instructions, instead of operation they are currently
used for.

llvm-svn: 99189

llvm-svn: 99187

specify encoding bits in arguments instead of "let" expressions.

llvm-svn: 99185

llvm-svn: 99182

llvm-svn: 99097

Patch by John Tytgat!

llvm-svn: 99096

with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095

address register writeback.

llvm-svn: 99094

rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.

llvm-svn: 99093

writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99090

llvm-svn: 99083

address register writeback.

llvm-svn: 99082

llvm-svn: 99081

rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.

llvm-svn: 99080

llvm-svn: 99078

load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.

llvm-svn: 99066

writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.

llvm-svn: 99065

llvm-svn: 99062

--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U    lib/Target/ARM/ARMInstrVFP.td

llvm-svn: 99049

load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

llvm-svn: 99043