No functional change (and no FE change to generate them).

llvm-svn: 55753

in FastISel.

llvm-svn: 55748

classes in the llvm namespace having members with types from
anonymous namespaces.

llvm-svn: 55747

HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.

This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.

llvm-svn: 55746

list that have internal linkage; the linker doesn't need
or want this.  (These objects must still be preserved
at compile time, so just removing them from the llvm.used
list doesn't work.)  Should affect only Darwin.

llvm-svn: 55722

llvm-svn: 55704

Fix an issue where we were reusing materializations of constants in blocks not dominated by the materialization.  This is
the simple fix, materializing the constant before every use.  It might be better to either track domination of uses or
to materialize all constants and the beginning of the function and let remat sort when to do materialization at uses.

llvm-svn: 55703

and SelectionDAGLowering classes, out of SelectionDAGISel.cpp and put
it in a separate file, SelectionDAGBuild.cpp.

llvm-svn: 55701

routines and move them into a separate file, ScheduleDAGEmit.cpp.

llvm-svn: 55699

when searching for redundant subregister dead/kill bits.

Previously it was common to see instructions marked like this:
  "RET %EAX<imp-use,kill>, %AX<imp-use,kill>"

With this change, addRegisterKilled continues scanning after
finding the %EAX operand, so it proceeds to discover the
redundant %AX kill and eliminates it, producing this:
  "RET %EAX<imp-use,kill>"

This currently has no effect on the generated code.

llvm-svn: 55698

llvm-svn: 55692

llvm-svn: 55668

even in FastISel mode in the case where FastISel successfully 
selects all the instructions. 

llvm-svn: 55641

The first can update the SDNode in an SDValue
while the second is called with SDNode* and
returns a possibly updated SDNode*.

This patch has no intended functional impact,
but helps eliminating ugly temporary SDValues.

llvm-svn: 55608

(what matters is that it is added to the worklist),
it seems more logical to return it.

llvm-svn: 55606

llvm-svn: 55578

llvm-svn: 55577

llvm-svn: 55576

   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotl x, y)
   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotr x, (sub 32, y))

Example: (x == 0xDEADBEEF and y == 4)

    (x << 4) | (x >> 28)
 => 0xEADBEEF0 | 0x0000000D
 => 0xEADBEEFD

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => 0xEADBEEFD

- Fix comment and code for second version. It wasn't using the rot* propertly.

   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
   //   (rotr x, y)
   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
   //   (rotl x, (sub 32, y))

    (x << 28) | (x >> 4)
 => 0xD0000000 | 0x0DEADBEE
 => 0xDDEADBEE

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => (0xEADBEEFD)

llvm-svn: 55575

llvm-svn: 55574

llvm-svn: 55571

Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.

llvm-svn: 55564

llvm-svn: 55563

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

llvm-svn: 55558

Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

llvm-svn: 55555

llvm-svn: 55551

llvm-svn: 55549

llvm-svn: 55512

llvm-svn: 55504

llvm-svn: 55500

its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498

SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

llvm-svn: 55497

were being emitted after the first instructions of the entry block.

llvm-svn: 55496

llvm-svn: 55483

Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.

llvm-svn: 55482

FastEmitInst_extractsubreg doesn't need to be passed the register class.  It can get it from MachineRegisterInfo instead.

llvm-svn: 55476

Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475

llvm-svn: 55471

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

llvm-svn: 55467

ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457