transformed to the final instruction variant. An
example would be dsrll which is transformed into 
dsll32 if the shift value is greater than 32.

For direct object output we need to do this transformation
in the codegen. If the instruction was inside branch
delay slot, it was being missed. This patch corrects this
oversight.

llvm-svn: 162779

traceback table on PowerPC64. This helps gdb handle exceptions. The other
mandatory fields are ignored by gdb and harder to implement so just add
there a FIXME.

Patch by Bill Schmidt. PR13641.

llvm-svn: 162778

Fix a couple of bugs in mips' long branch pass.
This patch was supposed to be committed along with r162731, so I don't have a
new test case.

llvm-svn: 162777

AsmStmts.  This function is only used by GCCAsmStmts, however. Constraints need
to be properly computed before MSAsmStmts can use EmitAsmStmt.  No functional
change intended.

llvm-svn: 162776

llvm-svn: 162775

While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

llvm-svn: 162774

llvm-svn: 162773

No test case since this is a debug option that we will never turn on by
default since it makes the leak checkers much less useful. (We'll only report
leaks at the end of analysis if -analyzer-purge=none.)

llvm-svn: 162772

llvm-svn: 162771

Register operands are manipulated by a lot of target-independent code,
and it is not always possible to preserve target flags. That means it is
not safe to use target flags on register operands.

None of the targets in the tree are using register operand target flags.
External targets should be using immediate operands to annotate
instructions with operand modifiers.

llvm-svn: 162770

llvm-svn: 162769

llvm-svn: 162768

character instead of always the last character.

llvm-svn: 162767

- The increment needs to be signed value to preserve the original value when
  its data type is larger than 64-bit integer.

llvm-svn: 162766

llvm-svn: 162765

Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

llvm-svn: 162764

This warns in two specific situations:

1) For potentially swapped function arguments, e.g.

     void foo(bool, float);
     foo(1.7, false);

2) Misplaced brackets around function call arguments, e.g.

     bool InRange = fabs(a - b < delta);

   Where the last argument in a function call is implicitly converted
   from bool to float, and the function returns a float which gets
   implicitly converted to bool.

Patch by Andreas Eckleder!

llvm-svn: 162763

llvm-svn: 162762

Path by Brooks Davis, tests and fixes from me.

llvm-svn: 162761

llvm-svn: 162760

llvm-svn: 162759

llvm-svn: 162758

llvm-svn: 162757

llvm-svn: 162756

No test case, undefined shifts get folded early, but can occur when other
transforms generate a constant. Thanks to Duncan for bringing this up.

llvm-svn: 162755

llvm-svn: 162754

llvm-svn: 162753

llvm-svn: 162752

llvm-svn: 162751

llvm-svn: 162750

Make sure that we don't call getZExtValue on values > 64 bits.
Thanks Benjamin for noticing this.

llvm-svn: 162749

llvm-svn: 162748

llvm-svn: 162747

llvm-svn: 162746

[asan] improve SetErrorReportCallbackTest to actually catch missing functionality in __asan_set_error_report_callback

llvm-svn: 162745

llvm-svn: 162744

Teach InstCombine to canonicalize  [SU]div+[AL]shl patterns.

For example:
  %1 = lshr i32 %x, 2
  %2 = udiv i32 %1, 100

rdar://12182093

llvm-svn: 162743

llvm-svn: 162742

it here, then a 'register-memory' version would wrongly get the commutative
flag.
<rdar://problem/12180135>

llvm-svn: 162741

llvm-svn: 162740