be used with fast-isel.

llvm-svn: 56268

When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.

llvm-svn: 56258

ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!

llvm-svn: 56253

Apologies for the thrashing.

llvm-svn: 56251

llvm-svn: 56250

- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249

MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.

llvm-svn: 56248

are not enabled. Instead just omit the tail call flag when calls are
created.

llvm-svn: 56235

Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.

llvm-svn: 56231

libcalls, as in this testcase on ARM.

llvm-svn: 56226

Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.

llvm-svn: 56199

llvm-svn: 56194

isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183

vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165

ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162

representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161

with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159

safe in the presence of NaNs.

llvm-svn: 56136

Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.

llvm-svn: 56118

llvm-svn: 56112

llvm-svn: 56097

llvm-svn: 56085

llvm-svn: 56069

llvm-svn: 56068

Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it.  This
was exposed by fast isel's handling of shifts on X86-64.  With this, FreeBench/pcompress2 passes on X86-64 in fast isel.

llvm-svn: 56067

to static allocas. As part of this change, refactor the
address mode code for laods and stores.

llvm-svn: 56066

llvm-svn: 56065

I shuffled the fast-isel command-line options around. This fixes
a bunch of fast-isel failures.

llvm-svn: 56057

llvm-svn: 56049

llvm-svn: 56048

llvm-svn: 56037

llvm-svn: 56036

form:

          powf(10.0f, x);

If this is the case, and also we want limited precision floating-point
calculations, then lower to do the limited-precision stuff.

llvm-svn: 56035

llvm-svn: 56032

to being off by default. Also, add assertion checks to check that
the various fast-isel-related command-line options are only used
when -fast-isel itself is enabled.

llvm-svn: 56029

llvm-svn: 56028

function.

llvm-svn: 56025

UsedDirective for some symbols in llvm.used into
Darwin-specific code.  I've decided LessPrivateGlobal
is potentially a useful abstraction and left it in
the target-independent area, with improved comment.

llvm-svn: 56024

floating-point numbers.

llvm-svn: 56023