to the landing pad. This will be used by the back-end to generate the jump
tables for dispatching the arriving longjmp in sjlj eh.

llvm-svn: 141224

"const char *" is NULL. Also cleaned up the display of strings when you have
an array of chars that are all NULL. Previously we were showing: ""...
We now show: ""

llvm-svn: 141223

and statics when no arguments are given. 

llvm-svn: 141222

llvm-svn: 141221

PhysReg operands are not allowed to have sub-register indices at all.

For virtual registers with sub-reg indices, check that all registers in
the register class support the sub-reg index.

llvm-svn: 141220

llvm-svn: 141219

llvm-svn: 141218

    watchpoint ignore -i <count> [<watchpt-id | watchpt-id-list>]

Add tests of watchpoint ignore_count for command line as well as API.

llvm-svn: 141217

llvm-svn: 141216

llvm-svn: 141215

llvm-svn: 141214

llvm-svn: 141213

The tool is called checkout_cloog.sh. We also update the get_started
documentation to include this tool. An older unfinished tool called
'get_cloog.sh' is removed to avoid confusion.

llvm-svn: 141212

line options.
 - <rdar://problem/10120602>, PR9631

llvm-svn: 141211

Just pull the instruction name, but don't change the order of anything
else. That keeps --debug happy and non-crashing, but doesn't change
how the worklist gets built.

llvm-svn: 141210

llvm-svn: 141209

Use APFloat::toString to print APFloats more precisely in the AST printer.  Patch by Olaf Krzikalla.  

llvm-svn: 141208

EXTRACT_SUBREG is emitted as %dst = COPY %src:sub, so there is no need to
constrain the %dst register class.  RegisterCoalescer will apply the
necessary constraints if it decides to eliminate the COPY.

The %src register class does need to be constrained to something with
the right sub-registers, though.  This is currently done manually with
COPY_TO_REGCLASS nodes.  They can possibly be removed after this patch.

llvm-svn: 141207

There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

llvm-svn: 141206

quoting code.

llvm-svn: 141205

fixes PR11038, but there are still some cleanups to be done.

llvm-svn: 141204

When updating the worklist for InstCombine, the Add/AddUsersToWorklist
functions may access the instruction(s) being added, for debug output for
example. If the instructions aren't yet added to the basic block, this
can result in a crash. Finish the instruction transformation before
adjusting the worklist instead.

rdar://10238555

llvm-svn: 141203

reasons.  However, it does seems practical to quote strings that need it.
rdar://10221951

llvm-svn: 141202

llvm-svn: 141201

from Manuel Holtgrewe!

llvm-svn: 141200

llvm-svn: 141199

The register class created by INSERT_SUBREG and SUBREG_TO_REG must be
legal and support the SubIdx sub-registers.

The new getSubClassWithSubReg() hook can compute that.

This may create INSERT_SUBREG instructions defining a larger register
class than the sub-register being inserted.  That is OK,
RegisterCoalescer will constrain the register class as needed when it
eliminates the INSERT_SUBREG instructions.

llvm-svn: 141198

llvm-svn: 141197

llvm-svn: 141196

llvm-svn: 141195

llvm-svn: 141194

llvm-svn: 141193

llvm-svn: 141190

llvm-svn: 141188

TwoAddressInstructionPass should annotate instructions with <undef>
flags when it lower REG_SEQUENCE instructions.  LiveIntervals should not
be in the business of modifying code (except for kill flags, perhaps).

llvm-svn: 141187

llvm-svn: 141184

llvm-svn: 141183

llvm-svn: 141182

llvm-svn: 141181

llvm-svn: 141180