llvm-svn: 55598

llvm-svn: 55597

llvm-svn: 55596

llvm-svn: 55594

llvm-svn: 55593

llvm-svn: 55591

llvm-svn: 55590

llvm-svn: 55588

instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.

llvm-svn: 55582

Dale, Could you please review this?

llvm-svn: 55581

combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.

llvm-svn: 55579

llvm-svn: 55578

llvm-svn: 55577

llvm-svn: 55576

   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotl x, y)
   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotr x, (sub 32, y))

Example: (x == 0xDEADBEEF and y == 4)

    (x << 4) | (x >> 28)
 => 0xEADBEEF0 | 0x0000000D
 => 0xEADBEEFD

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => 0xEADBEEFD

- Fix comment and code for second version. It wasn't using the rot* propertly.

   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
   //   (rotr x, y)
   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
   //   (rotl x, (sub 32, y))

    (x << 28) | (x >> 4)
 => 0xD0000000 | 0x0DEADBEE
 => 0xDDEADBEE

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => (0xEADBEEFD)

llvm-svn: 55575

llvm-svn: 55574

llvm-svn: 55571

Based on patch by Giorgos Korfiatis.

llvm-svn: 55570

Breakage was exposed in the Ocaml bindings tests after Chris
uncommented an assertion in r55084.

llvm-svn: 55566

llvm-svn: 55565

Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.

llvm-svn: 55564

llvm-svn: 55563

For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.

llvm-svn: 55562

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

llvm-svn: 55558

support it.

llvm-svn: 55557

llvm-svn: 55556

Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

llvm-svn: 55555

llvm-svn: 55554

llvm-svn: 55553

llvm-svn: 55552

llvm-svn: 55551

llvm-svn: 55550

llvm-svn: 55549

llvm-svn: 55548

llvm-svn: 55546

llvm-svn: 55545

llvm-svn: 55542

%4 = add ...

instead of:

add ...    ; 4

This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read.  This fixes PR2480

llvm-svn: 55541

llvm-svn: 55540

nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480

llvm-svn: 55539