llvm-svn: 130931

Avoid extra vreg copies for arguments passed in registers.  Specifically, this can make MachineCSE more effective in some cases (especially in small functions).  PR8361 / part of rdar://problem/8259436 .

llvm-svn: 130928

llvm-svn: 130926

llvm-svn: 130925

who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>

llvm-svn: 130918

Joining physregs is inherently dangerous because it uses a heuristic to avoid
creating invalid code. Linear scan had an emergency spilling mechanism to deal
with those rare cases. The new greedy allocator does not.

The greedy register allocator is much better at taking hints, so this has almost
no impact on code size and quality. The few cases where it matters show up as
unit tests that now have -join-physregs enabled explicitly.

llvm-svn: 130896

landing pad as its successor.

SjLj exception handling jumps to the correct landing pad via a switch statement
that's generated right before code-gen. Loosen the constraint in the machine
instruction verifier to allow for this. Note, this isn't the most rigorous check
since we cannot determine where that switch statement came from. But it's
marginally better than turning this check off when SjLj exceptions are used.
<rdar://problem/9187612>

llvm-svn: 130881

Original message:

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130877

llvm-svn: 130867

Teach MachineCSE how to do simple cross-block CSE involving physregs.  This allows, for example, eliminating duplicate cmpl's on x86. Part of rdar://problem/8259436 .

llvm-svn: 130862

it is both inefficient and unexpected by dwarfdump. Change to
a DW_FORM_data4.

While in here, change the predicate name to reflect that the position
is not really absolute (it is an offset), just that the linker needs a
relocation.

llvm-svn: 130846

Physreg joining is still on by default, but I will turn it off shortly.

llvm-svn: 130844

Tighten up check for empty (i.e. no meaningful debug info) module. This fixes dwarf-die2.c test case from gcc test suite.

llvm-svn: 130842

Even if the subprogram is going to use AT_specification, emit DW_AT_MIPS_linkage_name. This helps gdb and fixes var-path-expr.exp regression reported by gdb testsuite.

llvm-svn: 130794

Register coalescing can sometimes create live ranges that end in the middle of a
basic block without any killing instruction. When SplitKit detects this, it will
repair the live range by shrinking it to its uses.

Live range splitting also needs to know about this. When the range shrinks so
much that it becomes allocatable, live range splitting fails because it can't
find a good split point. It is paranoid about making progress, so an allocatable
range is considered an error.

The coalescer should really not be creating these bad live ranges. They appear
when coalescing dead copies.

llvm-svn: 130787

If the front end has emitted llvm.dbg.cu and other debug info anchors (clang does it now) then use them directly. This saves one scan of entire module, to collect debug info, which in turns saves few machine cycles at compile time.

llvm-svn: 130759

Other parts of the SelectionDAG framework assume that targets use their pointer type for vector indices.  Make the vector unrolling code respect that.

llvm-svn: 130733

llvm-svn: 130718

llvm-svn: 130715

Def operands may also have an <undef> flag, but that just means that a
sub-register redef doesn't actually read the super-register. For physical
registers, it has no meaning.

llvm-svn: 130714

This works around a limitation in gdb which is reported by following inherit.exp test failures from gdb testsuite.

gdb.cp/inherit.exp: print g_vB.vB::vb
gdb.cp/inherit.exp: print g_vB.vB::vx
gdb.cp/inherit.exp: print g_vC.vC::vc
gdb.cp/inherit.exp: print g_vC.vC::vx
gdb.cp/inherit.exp: print g_vD.vB::vb
...

llvm-svn: 130702

llvm-svn: 130692

When an interfering live range ends at a dead slot index between two
instructions, make sure that the inserted copy instruction gets a slot index
after the dead ones. This makes it possible to avoid the interference.

Ideally, there shouldn't be interference ending at a deleted instruction, but
physical register coalescing can sometimes do that to sub-registers.

This fixes PR9823.

llvm-svn: 130687

-fno-dwarf2-cfi-asm. Implement the same behavior.

llvm-svn: 130637

range covers the entire block.

The live range can't be terminated at a random instruction.

llvm-svn: 130619

This could happen when trying to use a value that had been eliminated after dead
code elimination and folding loads.

llvm-svn: 130597

llvm-svn: 130596

the final assembly. It is the same technique used when targeting
assemblers that don't support .loc.

llvm-svn: 130587

llvm-svn: 130582

llvm-svn: 130568

llvm-svn: 130562

Make FastEmit_ri_ try a bit harder to succeed for supported operations; FastEmit_i can fail for non-Thumb2 ARM.  Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM.

llvm-svn: 130560

Hoist MCLineEntry construction AsmPrinter so that anyone who derives from AsmPrinter can have line number entries.
PR 9810

llvm-svn: 130518

llvm-svn: 130504

emmits: .cfi_personality, .cfi_lsda and the moves.

llvm-svn: 130503

llvm-svn: 130501

This fixes clang generated blocks' variables' debug info.
Radar 9279956.

llvm-svn: 130373

llvm-svn: 130360

llvm-svn: 130343

give it a bit more responsibility. Also implement it for MachO.

If hacked to use cfi, 32 bit MachO will produce

.cfi_personality 155, L___gxx_personality_v0$non_lazy_ptr

and 64 bit will produce

.cfi_presonality ___gxx_personality_v0

The general idea is that .cfi_personality gets passed the final symbol. It is
up to codegen to produce it if using indirect representation (like 32 bit
MachO), but it is up to MC to decide which relocations to create.

llvm-svn: 130341