- May 10, 2012
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Andrew Trick authored
llvm-svn: 156576
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Andrew Trick authored
llvm-svn: 156575
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Andrew Trick authored
Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. llvm-svn: 156574
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Andrew Trick authored
llvm-svn: 156573
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Andrew Trick authored
llvm-svn: 156572
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Andrew Trick authored
llvm-svn: 156571
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Andrew Trick authored
Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. llvm-svn: 156561
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Andrew Trick authored
llvm-svn: 156560
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Manman Ren authored
This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
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Manman Ren authored
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
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- May 08, 2012
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Eric Christopher authored
Part of rdar://11352000 and should bring the buildbots back. llvm-svn: 156421
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Jim Grosbach authored
When a combine twiddles an extract_vector, care should be take to preserve the type of the index operand. No luck extracting a reasonable testcase, unfortunately. rdar://11391009 llvm-svn: 156419
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Akira Hatanaka authored
Patch by Jack Carter. llvm-svn: 156409
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Eric Christopher authored
Part of rdar://11352000 llvm-svn: 156405
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Jakob Stoklund Olesen authored
No functional change. llvm-svn: 156345
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Jakob Stoklund Olesen authored
llvm-svn: 156342
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Jakob Stoklund Olesen authored
At least some of them: %vreg1:sub_16bit = COPY %vreg2:sub_16bit; GR64:%vreg1, GR32: %vreg2 Previously, we couldn't figure out that the above copy could be eliminated by coalescing %vreg2 with %vreg1:sub_32bit. The new getCommonSuperRegClass() hook makes it possible. This is not very useful yet since the unmodified part of the destination register usually interferes with the source register. The coalescer needs to understand sub-register interference checking first. llvm-svn: 156334
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Jakob Stoklund Olesen authored
The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
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- May 07, 2012
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Owen Anderson authored
llvm-svn: 156324
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- May 05, 2012
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Benjamin Kramer authored
This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
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Jakob Stoklund Olesen authored
We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
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Jakob Stoklund Olesen authored
llvm-svn: 156219
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- May 04, 2012
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Jakob Stoklund Olesen authored
The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
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- May 03, 2012
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Evan Cheng authored
to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 llvm-svn: 156048
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Andrew Trick authored
The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. llvm-svn: 156046
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Owen Anderson authored
Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs. llvm-svn: 156029
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- May 02, 2012
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Owen Anderson authored
llvm-svn: 156023
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Jim Grosbach authored
llvm-svn: 155960
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Jakub Staszak authored
llvm-svn: 155957
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Bill Wendling authored
PR10799 llvm-svn: 155954
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- May 01, 2012
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Sirish Pande authored
llvm-svn: 155947
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Bill Wendling authored
The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 llvm-svn: 155902
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Jakub Staszak authored
llvm-svn: 155859
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- Apr 29, 2012
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Benjamin Kramer authored
llvm-svn: 155795
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- Apr 28, 2012
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Jakob Stoklund Olesen authored
We don't compute spill weights until after coalescing anyway. llvm-svn: 155766
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Jakob Stoklund Olesen authored
llvm-svn: 155765
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Andrew Trick authored
This time, also fix the caller of AddGlue to properly handle incomplete chains. AddGlue had failure modes, but shamefully hid them from its caller. It's luck ran out. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155749
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Andrew Trick authored
This definitely caused regression with ARM -mno-thumb. llvm-svn: 155743
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- Apr 26, 2012
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Andrew Trick authored
DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155668
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- Apr 25, 2012
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Jakob Stoklund Olesen authored
llvm-svn: 155566
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