llvm-svn: 106365

segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364

llvm-svn: 106361

llvm-svn: 106359

llvm-svn: 106358

llvm-svn: 106357

llvm-svn: 106356

on calls and similar instructions.

llvm-svn: 106353

llvm-svn: 106349

llvm-svn: 106327

llvm-svn: 106311

original basic block. This avoids trouble with examining
instructions in other basic blocks which haven't been
assigned registers yet.

llvm-svn: 106310

SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282

llvm-svn: 106280

llvm-svn: 106279

llvm-svn: 106278

llvm-svn: 106273

to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266

llvm-svn: 106264

which is faster, simpler, and less surprising.

llvm-svn: 106263

be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194

will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066

a relative address.

llvm-svn: 106064

flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.

llvm-svn: 106049

Nelson Elhage!

llvm-svn: 106031

llvm-svn: 105988

containing the target address, an input, into an output.  I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.

llvm-svn: 105986

symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954

more clear what exactly is missing.

llvm-svn: 105934

llvm-svn: 105900

llvm-svn: 105876

llvm-svn: 105873

llvm-svn: 105870

Handle OpSize TSFlag for AVX

llvm-svn: 105869

llvm-svn: 105860

Introduce the VEX_X field

llvm-svn: 105859

llvm-svn: 105674

instruction.  Added the 64-bit version "jrcxz" so it is recognized and also
added the checks for incorrect uses of "jcxz" in 64-bit mode and "jrcxz" in
32-bit mode.  Still to do is to correctly handle the encoding of the
instruction adding the Address-size override prefix byte, 0x67, when the width
of the count register is not the same as the mode the machine is running in.
Which for example means the encoding of "jecxz" depends if you are assembling
as a 32-bit target or a 64-bit target.

llvm-svn: 105661