bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091

direct inclusion edge from System to Support.

llvm-svn: 85086

llvm-svn: 85047

llvm-svn: 85046

Do not delete identity insert_subreg even if dest is virtual. Let later passes delete them. This avoids register scavenger complain.

llvm-svn: 85045

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

spill, it should avoid doing so inside the live range of a virtual register.

llvm-svn: 85026

used elsewhere - an exit block is a block outside the loop branched to
from within the loop. An exiting block is a block inside the loop that
branches out.

llvm-svn: 85019

llvm-svn: 84983

llvm-svn: 84978

the scale overflows pointer-sized arithmetic. This fixes PR5281.

llvm-svn: 84954

does.

llvm-svn: 84916

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

llvm-svn: 84911

llvm-svn: 84894

llvm-svn: 84806

to break up CFG diamonds by banishing one of the blocks to the end of
the function, which is bad for code density and branch size.

This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the
benchmark cited as the reason for the change, however I've examined
the code and it looks more like a case of gaming a particular
branch than of being generally applicable.

llvm-svn: 84803

llvm-svn: 84792

handles T2 and ARM use cases.

llvm-svn: 84761

llvm-svn: 84749

llvm-svn: 84727

Respect src register allocation requirements when breaking anti-dependencies. Remove some dead code.

llvm-svn: 84691

transform.

llvm-svn: 84683

llvm-svn: 84682

llvm-svn: 84681

llvm-svn: 84658

llvm-svn: 84657

of the register in the instruction which kills the scavenged value.

llvm-svn: 84641

tracked. Instead of trying to manually keep track of these locations
while doing complex modifications, just recompute them when they're needed.
This fixes a bug in which the TopMBB and BotMBB were not correctly updated,
leading to invalid transformations.

llvm-svn: 84598

llvm-svn: 84597

llvm-svn: 84596

llvm-svn: 84586

llvm-svn: 84585

appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.

llvm-svn: 84554

llvm-svn: 84516

llvm-svn: 84504

llvm-svn: 84503

llvm-svn: 84432

stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424

llvm-svn: 84411