llvm-svn: 146702

Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value.  (This is just to be safe; I don't think this actually causes any issues in practice.)

llvm-svn: 146700

llvm-svn: 146699

llvm-svn: 146692

llvm-svn: 146691

The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689

llvm-svn: 146686

llvm-svn: 146685

Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684

Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.

llvm-svn: 146671

llvm-svn: 146664

Patch by Kyriakos Georgiou.

llvm-svn: 146656

llvm-svn: 146627

rdar://10566486

llvm-svn: 146625

the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.

llvm-svn: 146612

An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

llvm-svn: 146609

llvm-svn: 146608

llvm-svn: 146605

Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594

llvm-svn: 146590

In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588

llvm-svn: 146585

r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.

llvm-svn: 146583

Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579

llvm-svn: 146575

emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572

llvm-svn: 146571

llvm-svn: 146570

llvm-svn: 146569

llvm-svn: 146568

When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567

llvm-svn: 146566

rdar://10549683

llvm-svn: 146543

  to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542

rdar://10549767

llvm-svn: 146520

rdar://10550269

llvm-svn: 146519

rdar://10549786

llvm-svn: 146518

llvm-svn: 146516

rdar://10549741

llvm-svn: 146515