and passes the real code to a memory-outputting code emitter. This may be
removed at a later point in development.

llvm-svn: 6379

MachineInstr can later be patched up correctly.

llvm-svn: 6378

llvm-svn: 6377

Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.

llvm-svn: 6376

Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.

This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.

llvm-svn: 6375

llvm-svn: 6373

llvm-svn: 6372

annotations on instructions to specify which format they are (i.e., do they take
2 registers and 1 immediate or just 3 registers) as that changes their binary
representation and hence, code emission.

This makes instructions more like how X86 defines them to be. Now, writers of
instruction selection must choose the correct opcode based on what instruction
type they are building, which they already know. Thus, the JIT doesn't have to
do the same work by `discovering' which operands an instruction really has.

As this involves lots of small changes to a lot of files in lib/target/Sparc,
I'll commit them individually because otherwise the diffs will be unreadable.

llvm-svn: 6371

specified as a static member in class definition.

llvm-svn: 6370

  a default value is set in the header file.
* Fixed some code layout to make it more consistent with the rest of codebase
* Added addPassesToJITCompile() with relevant passes

llvm-svn: 6369

* For debugging purposes:
  + output the predefined bit pattern of the instruction
* Fixed inefficiency: only load an operand from MachineInstr once
* Bug fix: did not advance bit index when seeing named bit-fields "annul", "cc"
  and "predict"
* Added a catch-all for non-supported instructions at the end of switch stmt.

llvm-svn: 6368

that Makefile.common would see it.

llvm-svn: 6367

Also, added annotations to how instructions are modified (reg/imm operands).
Added prototype for adding register numbers to values pass for interfacing with
the target-independent register allocators in the JIT.

llvm-svn: 6366

and to memory to test execution (using a passed-in code emitter).

llvm-svn: 6365

llvm-svn: 6364

MachineCodeEmitter to make a pass-through debugger -- output to memory and to
std::cerr.

llvm-svn: 6363

llvm-svn: 6362

of Sparc JIT (printing out instrs) on X86. Con: this increases linking time.

llvm-svn: 6361

`lli -march=x86' or `lli -march=sparc' will forcefully select the JIT even on a
different platform. Running lli without the -march option will select the JIT
for the platform that it's currently running on.

Pro: can test Sparc JIT (debug printing mode) on X86 -- faster to compile/link
LLVM source base to test changes.
Con: Linking lli on x86 now pulls in all the Sparc libs -> longer link time
(but X86 can bear it, right?)

In the future, perhaps this should be a ./configure option to enable/disable
target JITting...

llvm-svn: 6360

automatically in LLC

llvm-svn: 6358

that assembles instructions is generated via TableGen (and hence must be built
before building this directory, but that's already the case in the top-level
Makefile).

Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc',
which is included by SparcV9CodeEmitter.cpp .

llvm-svn: 6357

llvm-svn: 6356

llvm-svn: 6355

llvm-svn: 6354

llvm-svn: 6353

llvm-svn: 6352

llvm-svn: 6351

llvm-svn: 6350

* Implement SRoA for arrays

llvm-svn: 6349

llvm-svn: 6348

llvm-svn: 6347

llvm-svn: 6346

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

llvm-svn: 6343

and related functions and flags.  Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".

llvm-svn: 6342

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 6340

Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.

llvm-svn: 6339

llvm-svn: 6338

llvm-svn: 6337

llvm-svn: 6335